參數(shù)資料
型號(hào): XC3S400AN-5FTG256C
廠商: Xilinx Inc
文件頁(yè)數(shù): 36/123頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3AN
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計(jì): 368640
輸入/輸出數(shù): 195
門數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
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DS557 (v4.1) April 1, 2011
Product Specification
2
Copyright 2007–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Introduction
The Spartan-3AN FPGA family combines the best attributes
of a leading edge, low cost FPGA with nonvolatile technology
across a broad range of densities. The family combines all the
features of the Spartan-3A FPGA family plus leading
technology in-system Flash memory for configuration and
nonvolatile data storage.
The Spartan-3AN FPGAs are part of the Extended Spartan-3A
family, which also includes the Spartan-3A FPGAs and the
higher density Spartan-3A DSP FPGAs. The Spartan-3AN
FPGA family is excellent for space-constrained applications
such as blade servers, medical devices, automotive
infotainment, telematics, GPS, and other small consumer
products. Combining FPGA and Flash technology minimizes
chip count, PCB traces and overall size while increasing
system reliability.
The Spartan-3AN FPGA internal configuration interface is
completely self-contained, increasing design security. The
family maintains full support for external configuration. The
Spartan-3AN FPGA is the world’s first nonvolatile FPGA with
MultiBoot, supporting two or more configuration files in one
device, allowing alternative configurations for field upgrades,
test modes, or multiple system configurations.
Features
The new standard for low cost nonvolatile FPGA solutions
Eliminates traditional nonvolatile FPGA limitations with the
advanced 90 nm Spartan-3A device feature set
Memory, multipliers, DCMs, SelectIO, hot swap, power
management, etc.
Integrated robust configuration memory
Saves board space
Improves ease-of-use
Simplifies design
Reduces support issues
Plentiful amounts of nonvolatile memory available to the user
Up to 11+ Mb available
MultiBoot support
Embedded processing and code shadowing
Scratchpad memory
Robust 100K Flash memory program/erase cycles
20 years Flash memory data retention
Security features provide bitstream anti-cloning protection
Buried configuration interface
Unique Device DNA serial number in each device for
design Authentication to prevent unauthorized copying
Flash memory sector protection and lockdown
Configuration watchdog timer automatically recovers from
configuration errors
Suspend mode reduces system power consumption
Retains all design state and FPGA configuration data
Fast response time, typically less than 100
s
Full hot-swap compliance
Multi-voltage, multi-standard SelectIO interface pins
Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Up to 24 mA output drive
3.3V
10% compatibility and hot swap compliance
622+ Mb/s data transfer rate per I/O
DDR/DDR2 SDRAM support up to 400 Mb/s
LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL
differential I/O
Abundant, flexible logic resources
Densities up to 25,344 logic cells
Optional shift register or distributed RAM support
Enhanced 18 x 18 multipliers with optional pipeline
Hierarchical SelectRAM memory architecture
Up to 576 Kbits of dedicated block RAM
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Eight global clocks and eight additional clocks per each half
of device, plus abundant low-skew routing
Complete Xilinx ISE and WebPACK software
development system support
embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI technology support
Low-cost QFP and BGA Pb-free (RoHS) packaging options
Pin-compatible with the same packages in the
Spartan-3A FPGA family
9
Spartan-3AN FPGA Family:
Introduction and Ordering Information
DS557 (v4.1) April 1, 2011
Product Specification
Table 2: Summary of Spartan-3AN FPGA Attributes
Device
System
Gates
Equivalent
Logic
Cells
CLBs
Slices
Distributed
RAM
Bits(1)
Block
RAM
Bits(1)
Dedicated
Multipliers
DCMs
Maximum
User I/O
Maximum
Differential
I/O Pairs
Bitstream
Size(1)
In-System
Flash Bits
XC3S50AN
50K
1,584
176
704
11K
54K
3
2
144
64
427K
1M
XC3S200AN
200K
4,032
448
1,792
28K
288K
16
4
195
90
1,168K
4M
XC3S400AN
400K
8,064
896
3,584
56K
360K
20
4
311
142
1,842K
4M
XC3S700AN
700K
13,248
1,472
5,888
92K
360K
20
8
372
165
2,669K
8M
XC3S1400AN
1400K
25,344
2,816
11,264
176K
576K
32
8
502
227
4,644K
16M
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb.
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