參數(shù)資料
型號(hào)： XC3S400AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 95/123頁
文件大小： 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: Pinout Descriptions
DS557 (v4.1) April 1, 2011
Product Specification
73
Electronic versions of the package pinout tables and foot-prints are available for download from the Xilinx website at:
Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
Package Overview
Table 65 shows the five low-cost, space-saving production package styles for the Spartan-3AN family.
Each package style is available in an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an
extra “G” in the package style name. For example, the standard “CS484” package becomes “CSG484” when ordered as the
Pb-free option. Leaded (Pb) packages are available for selected devices, with the same pinout and without the “G” in the
ordering code; See Table 5, page 7 for more information. The mechanical dimensions of the Pb and Pb-free packages are
similar, as shown in the mechanical drawings provided in Table 66.
For additional package information, see UG112: Device Package User Guide.
Table 64: Maximum User I/O by Package
Device
Package
Maximum
User I/Os
and
Input-Only
Maximum
Input-
Only
Maximum
Differential
Pairs
All Possible I/Os by Type
I/O
INPUT
DUAL
VREF (1)
CLK
N.C.
XC3S50AN
TQG144
108
7
50
42
2
26
8
30
0
FTG256
144
32
64
53
20
26
15
30
51
XC3S200AN
FTG256
195
35
90
69
21
52
21
32
0
XC3S400AN
FTG256
195
35
90
69
21
52
21
32
0
FGG400
311
63
142
155
46
52
26
32
0
XC3S700AN
FGG484
372
84
165
194
61
52
33
32
3
XC3S1400AN
FGG484
375
87
165
195
62
52
34
32
0
FGG676
502
94
227
313
67
52
38
32
17
Notes:
1.
Some VREFs are on INPUT pins. See pinout tables for details.
Table 65: Spartan-3AN Family Package Options
Package
Leads
Type
Maximum I/Os
Lead Pitch
(mm)
Body Area
(mm)
Height
(mm)
TQ144/TQG144
144
Thin Quad Flat Pack (TQFP)
108
0.5
20 x 20
1.60
FT256/FTG256
256
Fine-pitch Thin Ball Grid Array (FBGA)
195
1.0
17 x 17
1.55
FG400/FGG400
400
Fine-pitch Ball Grid Array (FBGA)
311
1.0
21 x 21
2.43
FG484/FGG484
484
Fine-pitch Ball Grid Array (FBGA)
375
1.0
23 x 23
2.60
FG676/FGG676
676
Fine-pitch Ball Grid Array (FBGA)
502
1.0
27 x 27
2.60
Notes:
1.
For mass, refer to the MDDS files (see Table 66).
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