參數(shù)資料
型號： XC3S400AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 75/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
55
Table 42: Switching Characteristics for the DFS
Symbol
Description
Device
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX
Frequency for the CLKFX and CLKFX180 outputs
All
5
350
5
320
MHz
Output Clock Jitter (2)(3)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs.
CLKIN
20 MHz
All
Typ
Max
Typ
Max
Use the Spartan-3A Jitter
Calculator:
ps
CLKIN
> 20 MHz
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
Duty Cycle(4)(5)
CLKOUT_DUTY_CYCLE_FX
Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
–±[1% of
CLKFX
period
+ 350]
–±[1% of
CLKFX
period
+ 350]
ps
Phase Alignment(5)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX
output and the DLL CLK0 output when
both the DFS and DLL are used
All
–±200
ps
CLKOUT_PHASE_FX180 Phase offset between the DFS
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
are used
All
–±[1% of
CLKFX
period
+ 200]
–±[1% of
CLKFX
period
+ 200]
ps
Lock Time
LOCK_FX(2)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
5 MHz < FCLKIN
< 15 MHz
All
–5
ms
FCLKIN >
15 MHz
–450
–
450
s
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 41.
2.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA.
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
4.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
5.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
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