參數(shù)資料
型號： XC3S400AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 31/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
15
General DC Characteristics for I/O Pins
Table 11: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max
Units
IL(2)
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN =0V or VCCO max, sample-tested
–10
–
+10
A
IHS
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
A
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
Add IHS + IRPU
A
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.(4)
VIN = GND
VCCO or VCCAUX =
3.0V to 3.6V
–151
–315
–710
A
VCCO = 2.3V to 2.7V
–82
–182
–437
A
VCCO = 1.7V to 1.9V
–36
–88
–226
A
VCCO = 1.4V to 1.6V
–22
–56
–148
A
VCCO = 1.14V to 1.26V
–11
–31
–83
A
RPU(3)
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 3)
VIN = GND
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
k
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
k
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
k
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
k
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
k
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
VIN = VCCO
VCCAUX = 3.0V to 3.6V
167
346
659
A
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 3)
VCCAUX = 3.0V to 3.6V
VIN = 3.0V to 3.6V
5.5
10.4
20.8
k
VIN = 2.3V to 2.7V
4.1
7.8
15.7
k
VIN = 1.7V to 1.9V
3.0
5.7
11.1
k
VIN = 1.4V to 1.6V
2.7
5.1
9.6
k
VIN = 1.14V to 1.26V
2.4
4.5
8.1
k
IREF
VREF current per pin
All VCCO levels
–10
–
+10
A
CIN
Input capacitance
–
–10
pF
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
VCCO = 3.3V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
VCCO = 2.5V ± 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Notes:
1.
The numbers in this table are based on the conditions set forth in Table 10.
2.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
3.
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD =VIN /IRPD.
4.
VCCAUX must be 3.3V on Spartan-3AN FPGAs. VCCAUX for Spartan-3A FPGAs can be either 3.3V or 2.5V.
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