參數(shù)資料
型號(hào)： XPC755BRX400LE
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 1274K
代理商： XPC755BRX400LE
16
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a
socketed part on a functional tester at the maximum frequencies of Table 11. Therefore, functional operation
and AC timing information are tested at core-to-L2 divisors of 2 or greater. Functionality of core-to-L2
divisors of 1 or 1.5 is verified at less than maximum rated frequencies.
L2 input and output signals are latched or enabled, respectively, by the internal L2CLK (which is SYSCLK
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC
timings of Table 12 and Table 13 are entirely independent of L2SYNC_IN. In a closed loop system, where
L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output
phase of L2CLK_OUTA and L2CLK_OUTB which are used to latch or enable data at the SRAMs.
However, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK,
the signals of Table 12 and Table 13 are referenced to this signal rather than the not-externally-visible
internal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK.
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the
L2SYNC_IN input of the MPC755 to synchronize L2CLK_OUT at the SRAM with the processor’s internal
clock. L2CLK_OUT at the SRAM can be offset forward or backward in time by shortening or lengthening
the routing of L2SYNC_OUT to L2SYNC_IN. See Motorola Application Note AN179/D,
PowerPC
Backside L2 Timing Analysis for the PCB Design Engineer
.
The L2CLK_OUTA and L2CLK_OUTB signals should not have more than two loads.
Table 11. L2CLK Output AC Timing Specification
At recommended operating conditions (see Table 3)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2CLK frequency
f
L2CLK
t
L2CLK
80
450
MHz
1, 4
L2CLK cycle time
2.5
12.5
ns
L2CLK duty cycle
t
CHCL
/t
L2CLK
50
%
2, 7
Internal DLL-relock time
640
—
L2CLK
3, 7
DLL capture window
0
10
ns
5, 7
L2CLK_OUT output-to-output skew
t
L2CSKW
—
50
ps
6, 7
L2CLK_OUT output jitter
—
±150
ps
6, 7
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT, and L2SYNC_OUT pins. The L2CLK frequency
to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not
exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be
system dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL-relock time is specified in terms of L2CLK periods. The number in the table must be multiplied by the
period of L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and
characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap
of the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL
tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal
L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects
L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already comprehended in the AC
timing and does not have to be considered in the L2 timing analysis.
7. Guaranteed by design and characterization.
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