參數(shù)資料
型號： XPC755BRX400LE
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 29/52頁
文件大小： 1274K
代理商： XPC755BRX400LE
MOTOROLA
MPC755 RISC Microprocessor Hardware Specifications
29
Package Description
1.7
Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC745, 255
PBGA package, as well as the MPC755, 360 CBGA and PBGA packages. While both the MPC755 plastic
and ceramic packages are described here, both packages are not guaranteed to be available at the same time.
All new designs should allow for either ceramic or plastic BGA packages for this device. For more
information on designing a common footprint for both plastic and ceramic package types, see the
Motorola
Flip-Chip Plastic Ball Grid Array Presentation
. The MPC755 was initially sampled in a CBGA package,
but production units are currently provided in both a CBGA and a PBGA package. Because of the better
long-term device-to-board interconnect reliability of the PBGA package, Motorola recommends use of a
PBGA package except where circumstances dictate use of a CBGA package.
1.7.1
Package Parameters for the MPC745 PBGA
The package parameters are as provided in the following list. The package type is 21
×
21 mm, 255-lead
plastic ball grid array (PBGA).
Package outline
21
×
21 mm
Interconnects
255 (16
×
16 ball array
– 1)
Pitch
1.27 mm (50 mil)
Minimum module height
2.25 mm
Maximum module height 2.80 mm
Ball diameter (typical)
0.75 mm (29.5 mil)
VOLTDET
K13
High
Output
L2OV
DD
8
Notes:
1. OV
DD
supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE,
L2WE, and L2ZZ); L2OV
DD
supplies power to the L2 cache interface (L2ADDR[0:16], L2DATA[0:63], L2DP[0:7],
and L2SYNC_OUT) and the L2 control signals; and V
DD
supplies power to the processor core and the PLL and
DLL (after filtering to become AV
DD
and L2AV
DD
, respectively). These columns serve as a reference for the
nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 2 and
the voltage supplied. For actual recommended value of V
in
or supply voltages, see Table 3.
2. These are test signals for factory use only and must be pulled up to OV
DD
for normal machine operation.
3. This pin must be pulled up to OV
DD
for proper operation of the processor interface. To allow for future I/O voltage
changes, provide the option to connect BVSEL independently to either OV
DD
or GND.
4. These pins are reserved for potential future use as additional L2 address pins.
5. Uses one of nine existing no connects in MPC750, 360 BGA package.
6. Internal pull-up on die.
7. This pin must be pulled up to L2OV
DD
for proper operation of the processor interface. To allow for future I/O
voltage changes, provide the option to connect L2VSEL independently to either L2OV
DD
or GND.
8. Internally tied to L2OV
DD
in the MPC755, 360 BGA package to indicate the power present at the L2 cache
interface. This signal is not a power supply input.
Caution:
This differs from the MPC745, 255 BGA package.
Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Voltage
1
Notes
相關(guān)PDF資料
PDF描述
XPC750EC XPC750P/D XPC750P RISC Microprocessor Hardware Specifications
XPC801ZP25 Microprocessor
XPC801ZP40 Microprocessor
XPC821ZP40 Microprocessor
XPC823ZP25 Microprocessor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XPC801ZP25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
XPC801ZP40 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
XPC821ZP40 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
XPC823CVR66B2T 功能描述:IC MPU POWERQUICC 66MHZ 256-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC8xx 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤
XPC823CZC66A 制造商:Freescale Semiconductor 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*