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參數(shù)資料
| 型號： | XPC755BRX400LE |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | XPC755BRX400LE |
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34
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
System Design Information
The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC755. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the MPC755 to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin
L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking
of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the MPC755 core, and the phase adjustment range that the L2 DLL supports. Table 17 shows
various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum
L2 frequency target is 80 MHz.
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC755; see Section 1.4.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.
Note:
The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL off mode, no clocking occurs inside the MPC755 regardless of the SYSCLK input.
Table 17. Sample Core-to-L2 Frequencies
Core Frequency (MHz)
÷1
÷1.5
÷2
÷2.5
÷3
250
266
275
300
325
333
350
366
375
400
433
450
250
266
275
300
325
333
350
366
375
400
433
450
166
177
183
200
217
222
233
244
250
266
288
300
125
133
138
150
163
167
175
183
188
200
217
225
100
106
110
120
130
133
140
146
150
160
173
180
83
89
92
100
108
111
117
122
125
133
144
150
Note:
The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not
tested for by the MPC755; see Section 1.4.2.3, “L2 Clock AC Specifications,” for
valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK
frequencies less than 110 MHz.
Table 16. MPC755 Microprocessor PLL Configuration Example for 450 MHz Parts (continued)
PLL_CFG
[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
33 MHz
Bus
50 MHz
Bus
66 MHz
Bus
75 MHz
Bus
80 MHz
Bus
100 MHz
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