參數(shù)資料
型號(hào)： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 122/149頁
文件大?。?/td> 1274K
代理商： XRT86VL3X
XRT86VL3X
115
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
9.5
T1 Extended Superframe Format (ESF)
In Extended Superframe Format (ESF), as shown in
Figure 104
and
Table 11
, the multiframe structure is
extended to 24 frames. The timeslot structure is identical to D4 (SF) format. Robbed-bit signaling is
accommodated in frame 6 (A-bit), frame 12 (B-bit), frame 18 (C-bit) and frame 24 (D-bit).
The F-bit pattern of ESF contains three functions:
1.
Framing Pattern Sequence (FPS), which defines the frame and multiframe boundaries.
2.
Facility Data Link (FDL), which allows data such as error-performance to be passed within the T1 link.
3.
Cyclic Redundancy Check (CRC), which allows error performance to be monitored and enhances the reli-
ability of the receiver’s framing algorithm.
9
1544
1
----
1-8
----
----
10
1737
----
1
1-8
----
----
11
1930
0
----
1-8
----
----
12
2123
----
0
1-7
8
B
F
IGURE
104. T1 E
XTENDED
S
UPERFRAME
F
ORMAT
T
ABLE
10: S
UPERFRAME
F
ORMAT
F
RAME
B
IT
F-B
ITS
B
IT
U
SE
IN
E
ACH
T
IMESLOT
S
IGNALLING
C
HANNEL
T
ERMINAL
F
RAMING
F
T
T
ERMINAL
F
RAMING
F
S
T
RAFFIC
S
IG
D
C
CRC
FD
L
FP
S
r
s
CRC
FD
L
FPS
or
Fs
B
A
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
8 Bits per
Timeslot
TS
1
TS
1
TS
2
TS
2
-----------------
-
-----------------
TS
13
TS
13
------------------
-
------------------
TS
24
TS
24
FR
1
FR
1
FR
2
FR
2
-----------------
-
-----------------
FR
13
FR
13
------------------
-
------------------
FR
23
FR
23
FR
24
FR
24
Signalling
Information
Bit 7
During:
Frame 24
Frame 18
Frame 12
Frame 6
24 Timeslots per Frame
Frame = 193 Bits
Multiframe
ESF = 24
Frames
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