參數(shù)資料
型號(hào)： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 83/149頁
文件大小： 1274K
代理商： XRT86VL3X
XRT86VL3X
76
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
The following table illustrates how payload bits and signaling bits are multiplexed together into the 16.384Mbit/
s data stream.
X
Y
: The Xth payload bit of Channel Y
A
Y
: The signaling bit A of Channel Y
5.
After payload bits of Timeslot 0, 1 and 2 of all four channels are sent, the Terminal Equipment should stuff
another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream.
6.
Following the same rules of Step 2 to 5, the local Terminal Equipment stuffs eight octets of "don't care" data
after sending twenty-four octets of multiplexed payload and signaling data. A 16.384Mbit/s data stream is
thus created.
The Transmit Single-frame Synchronization signal of Channel 0 pulses HIGH for one clock cycle at the first bit
position (F-bit of channel 0) of the data stream with data from Channel 0-3 multiplexed together. The Transmit
Single-frame Synchronization signal of Channel 4 pulses HIGH for one clock cycle at the first bit position (F-bit
of Channel 4) of the data stream with data from Channel 4-7 multiplexed together. By sampling the HIGH pulse
on the Transmit Single-frame Synchronization signal, the framer can position the beginning of the multiplexed
DS1 frame. It is responsibility of the Terminal Equipment to align the multiplexed transmit serial data with the
Transmit Single-frame Synchronization pulse.
Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are
de-multiplexed inside the XRT86VL3x and send to each individual channel. These data will be processed by
each individual framer and send to LIU interface. The local Terminal Equipment provides a free-running
1.544MHz clock to the Transmit Serial Input clock of each channel. The framer will use this clock to carry the
processed payload and signaling data to the transmit section of the device.
Figure shows the timing signal when the transmit framer is running at 16.384 Bit-Multiplexed mode.
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
5
0
A
0
5
1
A
1
5
2
A
2
5
3
A
3
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
6
0
B
0
6
1
B
1
6
2
B
2
6
3
B
3
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
7
0
C
0
7
1
C
1
7
2
C
2
7
3
C
3
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
8
0
D
0
8
1
D
1
8
2
D
2
8
3
D
3
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