參數資料
型號： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數： 34/149頁
文件大?。?/td> 1274K
代理商： XRT86VL3X
XRT86VL3X
27
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
2.10
D/E Time Slot Transmit HDLC Controller Block V5.1 or V5.2 Interface
V5.2 protocol specifies a provision for transmitting simultaneous LAPD messages. Since only one message
can be sent through the datalink bits at one time, an alternative path for communication is offered within the
framer block. This alternative path is known as D or E channel which can be transmitted through one or more
of the DS-0 time slots. D channel is used primarily for data link applications. E channel is used primarily for
signaling for circuit switching with multiple access configurations. A range of time slots can be dedicated to
HDLC1, while a different range of time slots can be dedicated to HDLC2 to support V5.2. In addition, HDLC3
can be used to transmit a third LAPD message if desired. The HDLC controllers are implemented in the same
manner as the datalink described above with the exception of the data link source select bits.
2.11
Automatic Performance Report (APR)
The APR feature allows the system to transmit PMON status within a LAPD Framing format A at one second
intervals or within a single shot report. The data octets 5 through 12 within the LAPD frame are replaced with
the PMON status for the previous one second interval.
N
OTE
:
The right most bit (bit 1) is transmitted first for all fields except for the two bytes of the FCS that are transmitted left
most bit (bit 8) first.
2.11.1
Bit Value Interpretation
G1 = 1 if number of CRC error events is equal to 1
G2 = 1 if number of CRC error events is greater than 1 or equal to 5
G3 = 1 if number of CRC error events is greater than 5 or equal to 10
G4 = 1 if number of CRC error events is greater than 10 or equal to 100
G5 = 1 if number of CRC error events is greater than 100 or equal to 319
G6 = 1 if number of CRC error events is equal to 320
SE = 1 if a severely errored framing event occurs (FE shall be 0)
FE = 1 if a framing synchronization bit error event occurs (SE shall be 0)
LV = 1 if a line code violation event occurs
SL = 1 if slip event within the slip buffer occurs
T
ABLE
2: F
RAMING
F
ORMAT
FOR
PMON S
TATUS
I
NSERTED
WITHIN
LAPD
BY
I
NITIATING
APR
Octet Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
7
6
5
4
3
2
1
Time (s)
CR
EA=0
EA=1
G3
FE
G3
FE
G3
FE
G3
FE
LV
SE
LV
SE
LV
SE
LV
SE
G4
LB
G4
LB
G4
LB
G4
LB
U1
G1
U1
G1
U1
G1
U1
G1
U2
R
U2
R
U2
R
U2
R
G5
G2
G5
G2
G5
G2
G5
G2
SL
Nm
SL
Nm
SL
Nm
SL
Nm
G6
Ni
G6
Ni
G6
Ni
G6
Ni
T
0
T
0
- 1
T
0
- 2
T
0
- 3
Flag = 01111110
SAPI = 001110
TEI = 0000000
Control = 00000011 = Unacknowledged Frame
FCS
FCS
Flag = 01111110
相關PDF資料
PDF描述
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