參數(shù)資料
型號： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 85/149頁
文件大?。?/td> 1274K
代理商： XRT86VL3X
XRT86VL3X
78
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
X
Y
: The Xth payload bit of Channel Y
4.
When the framer is running at HMVIP 16.384MBit/s byte-mulitplexed mode, signaling information is
inserted from the TxSig/TxCHN[0] pin or from the TSCR register (0xn340-n357). When the local terminal
is sending the fifth payload bit of one channel, signaling bit A of that corresponding channel is repeated
and sent through the TxSig/TxCHN[0] pin; Similarly, signaling bit B, C, and D of the corresponding channel
is repeated and sent through the TxSig/TxCHN[0] pin when the local terminal is providing the sixth, sev-
enth, and eighth payload bit respectively, as shown in
Figure
.
5.
After payload bits of Timeslot 0, 1 and 2 of all four channels are sent, the Terminal Equipment should stuff
another eight octets (sixty-four bits) of "don't care" data into the outgoing data stream.
6.
Following the same rules of Step 2 to 5, the local Terminal Equipment stuffs eight octets of "don't care" data
after sending twenty-four octets of multiplexed payload and signaling data. A 16.384Mbit/s data stream is
thus created.
For HMVIP mode, the Transmit Single-frame Synchronization signal should pulse HIGH for four clock cycles
(the last two bit positions of the previous multiplexed frame and the first two bits of the next multiplexed frame)
indicating frame boundary of the multiplexed data stream. For H.100 mode, TxSYNC should pulse HIGH for
two clock cycles (the last bit position of the previous multiplexed frame and the first bit of the next multiplexed
frame). The Transmit Single-frame Synchronization signal of Channel 0 pulses HIGH to identify the start of
multiplexed data stream of Channel 0-3. The Transmit Single-frame Synchronization signal of Channel 4
pulses HIGH to identify the start of multiplexed data stream of Channel 4-7. By sampling the HIGH pulse on the
Transmit Single-frame Synchronization signal, the framer can position the beginning of the multiplexed DS1
frame. It is responsibility of the Terminal Equipment to align the multiplexed transmit serial data with the
Transmit Single-frame Synchronization pulse.
Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are
de-multiplexed inside the XRT86VL3x and send to each individual channel. These data will be processed by
each individual framer and send to LIU interface. The local Terminal Equipment provides a free-running
1.544MHz clock to the Transmit Serial Input clock of each channel. The framer will use this clock to carry the
processed payload and signaling data to the transmit section of the device.
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
3
1
3
2
3
2
3
3
3
3
3
4
3
4
3
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