參數(shù)資料
型號： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 40/149頁
文件大小： 1274K
代理商： XRT86VL3X
XRT86VL3X
33
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
3.2
DS1 Receive Overhead Output Interface Block
3.2.1
Description of the DS1 Receive Overhead Output Interface Block
The DS1 Receive Overhead Output Interface Block allows an external device to be the consumer of the
Facility Data Link (FDL) bits in ESF framing format mode, Signaling Framing (Fs) bits in the SLC96 and N
framing format mode and Remote Signaling (R) bit in T1DM framing format mode This interface provides
interface signals and required interface timing to shift out proper data link information at proper time.
The Receive Overhead Output Interface for a given Framer consists of two signals.
RxOHClk_n: The Receive Overhead Output Interface Clock Output signal
RxOH_n: The Receive Overhead Output Interface Output signal.
The Receive Overhead Output Interface Clock Output pin (RxOHCLK_n) generates a rising clock edge for
each data link bit position according to configuration of the framer. The data link bits extracted from the
incoming T1 frames are outputted from the Receive Overhead Output Interface Output pin (RxOH_n) at the
rising edge of RxOHClk_n. The Data Link equipment should sample and latch the data link bits at the falling
edge of RxOHClk_n.
The figure below shows block diagram of the Receive Overhead Output Interface of XRT86VL3x.
3.2.2
Configure the DS1 Receive Overhead Output Interface module as destination of the Facility
Data Link (FDL) bits in ESF framing format mode
The FDL bits in ESF framing format mode can be extracted to:
DS1 Receive Overhead Output Interface Block
DS1 Receive HDLC Controller
DS1 Receive Serial Output Interface.
The Receive Data Link Source Select bits of the Receive Data Link Select Register (RDLSR) controls the
extraction of FDL bits in ESF framing format mode. The table below shows configuration of the Receive Data
Link Source Select bits of the Receive Data Link Select Register (RDLSR).
F
IGURE
34. B
LOCK
D
IAGRAM
OF
THE
DS1 R
ECEIVE
O
VERHEAD
O
UTPUT
I
NTERFACE
OF
XRT86VL3
X
Receive
Overhead Output
Interface
RxOH_n
RxOHClk_n
From Receive
Framer Block
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