參數(shù)資料
型號： XRT86VL3X
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 74/149頁
文件大?。?/td> 1274K
代理商： XRT86VL3X
XRT86VL3X
67
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
7.0
THE DS1 TRANSMIT/RECEIVE FRAMER
7.1
Description of the Transmit/Receive Payload Data Input Interface Block
Each of the four framers within the XRT86VL3x device includes a Transmit and Receive Payload Data Input
Interface block. Although most configurations are independent for the Tx and Rx path, once T1 framing has
been selected, both the Tx and Rx must operate in T1. The Payload Data Input Interface module (also known
as the Back-plane Interface module) supports payload data to be taken from or presented to the system. In T1
modes, supported data rates are 1.544Mbit/s, MVIP 2.048Mbit/s, 4.096Mbit/s, 8.192Mbit/s, multiplexed
12.352Mbit/s, 16.384Mbit/s, HMVIP 16.384Mbit/s, or H.100 16.384Mbit/s.
7.1.1
Brief Discussion of the Transmit/Receive Payload Data Input Interface Block Operating at
1.544Mbit/s mode
Whether or not the transmit/receive interface signals have been chosen as inputs or outputs, the overall
system timing diagrams remain the same. It is the responsibility of the Terminal Equipment to provide serial
input data through the TxSER pin aligned with the Transmit Single-frame Synchronization signal and the
Transmit Multi-frame Synchronization signal.
Figure 73
shows how to connect the Transmit Payload Data
Input Interface block to local Terminal Equipment.
Figure 74
shows how to connect the Receive Payload Data
Output Interface to local Terminal Equipment.
F
IGURE
73. I
NTERFACING
THE
T
RANSMIT
P
ATH
TO
LOCAL
TERMINAL
EQUIPMENT
TxSERCLK0
TxSER0
TxMSYNC0
TxSYNC0
TxCHCLK0
TxCHN[4:0]_0
TxSERCLKn
TxSERn
TxMSYNCn
TxSYNCn
TxCHCLKn
TxCHN[4:0]_n
Transmit
Payload
Data Input
Interface
Chn 0
Transmit
Payload
Data Input
Interface
Chn N
Terminal
Equipment
XRT86VL3x
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