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參數(shù)資料
| 型號： | XRT86VL3X |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 8/149頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
V
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
Figure 58.: Interfacing the Receive Path to local terminal equipment ..............................................................................55
Figure 60.: Waveforms for connecting the Receive Payload Data Input Interface Block to local Terminal Equipment ...56
Figure 61.: Transmit Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP 2.048Mbit/s,
4.096Mbit/s, or 8.192Mbit/s ...............................................................................................................................57
Figure 62.: Receive Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP 2.048Mbit/s,
4.096Mbit/s, or 8.192Mbit/s ...............................................................................................................................57
Figure 63.: Waveforms for Connecting the Transmit Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/s,
4.096Mbit/s, and 8.192Mbit/s ............................................................................................................................58
Figure 64.: Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/s,
4.096Mbit/s, and 8.192Mbit/s ............................................................................................................................58
Figure 65.: Interfacing XRT86VL3x Transmit to local terminal equipment using 16.384Mbit/s, HMVIP 16.384Mbit/s, and
H.100 16.384Mbit/s ...........................................................................................................................................62
Figure 66.: Timing signal when the framer is running at Bit-Multiplexed 16.384Mbit/s mode ..........................................62
Figure 67.: Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at HMVIP And H.100
16.384Mbit/s mode ............................................................................................................................................63
Figure 68.: Interfacing XRT86VL3x Receive to local terminal equipment using 16.384Mbit/s, HMVIP 16.384Mbit/s, and
H.100 16.384Mbit/s ...........................................................................................................................................64
Figure 69.: Timing Signal When the Receive Framer is running at 16.384MHz Bit-Mulitplexed Mode ...........................64
Figure 70.: Timing Signal wehn the Receive Framer is Running at HMVIP and H100 16.384MHz Mode ......................64
Figure 71.: Timing Diagram of the TxSIG Input ...............................................................................................................66
Figure 72.: Timing Diagram of the RxSIG Output ............................................................................................................66
Figure 73.: Interfacing the Transmit Path to local terminal equipment .............................................................................67
Figure 75.: Waveforms for connecting the Transmit Payload Data Input Interface Block to local Terminal Equipment ..68
Figure 74.: Interfacing the Receive Path to local terminal equipment ..............................................................................68
Figure 76.: Waveforms for connecting the Receive Payload Data Input Interface Block to local Terminal Equipment ...69
Figure 77.: Transmit Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP 2.048Mbit/s,
4.096Mbit/s, or 8.192Mbit/s ...............................................................................................................................70
Figure 79.: Waveforms for Connecting the Transmit Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/s,
4.096Mbit/s, and 8.192Mbit/s ............................................................................................................................71
Figure 78.: Receive Non-Multiplexed High-Speed Connection to local terminal equipment using MVIP 2.048Mbit/s,
4.096Mbit/s, or 8.192Mbit/s ...............................................................................................................................71
Figure 80.: Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/s,
4.096Mbit/s, and 8.192Mbit/s ............................................................................................................................72
Figure 81.: Interfacing XRT86VL3x Transmit to local terminal equipment using 16.384Mbit/s, HMVIP 16.384Mbit/s, and
H.100 16.384Mbit/s ...........................................................................................................................................74
Figure 82.: Timing Signals When the Transmit Framer is Running at 12.352 Bit-Multiplexed Mode ...............................75
Figure 83.: Timing signals when the transmit framer is running at 16.384 Bit-Multiplexed mode ....................................77
Figure 84.: Timing signals when the transmit framer is running at HMVIP / H.100 16.384MHz Mode ............................79
Figure 85.: Interfacing XRT86VL3x Receive to local terminal equipment using 16.384Mbit/s, HMVIP 16.384Mbit/s, and
H.100 16.384Mbit/s ...........................................................................................................................................80
Figure 86.: Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at 12.352Mbit/s mode .....80
Figure 87.: Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at 16.384Mbit/s mode .....80
Figure 88.: Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at HMVIP and H.100 16.384Mbit/
s mode ...............................................................................................................................................................81
Figure 89.: Timing Diagram of the TxSig_n Input ............................................................................................................83
Figure 90.: Simple Diagram of E1 system model .............................................................................................................93
Figure 91.: Generation of Yellow Alarm by the Repeater upon detection of line failure ..................................................94
Figure 92.: Generation of AIS by the Repeater upon detection of line failure ..................................................................95
Figure 93.: Generation of Yellow Alarm by the CPE upon detection of AIS originated by the Repeater .........................96
Figure 94.: Generation of CAS Multi-frame Yellow Alarm and AIS16 by the Repeater ...................................................97
Figure 95.: Generation of CAS Multi-frame Yellow Alarm by the CPE upon detection of “AIS16” pattern sent by the Repeater
98
Figure 96.: Simple Diagram of DS1 System Model .......................................................................................................101
Figure 97.: Generation of Yellow Alarm by the CPE upon detection of line failure ........................................................102
Figure 98.: Generation of Yellow Alarm by the CPE upon detection of AIS originated by the Repeater .......................104
Figure 99.: Single E1 Frame Diagram ...........................................................................................................................108
Figure 100.: Frame/Byte Format of the CAS Multi-Frame Structure ..............................................................................111
Figure 101.: E1 Frame Format .......................................................................................................................................112
Figure 102.: T1 Frame Format .......................................................................................................................................113
Figure 103.: T1 Superframe PCM Format .....................................................................................................................114
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| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
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| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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