- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376464 > XRT86VL3X (Exar Corporation) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT86VL3X |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 28/149頁(yè) |
| 文件大小： | 1274K |
| 代理商： | XRT86VL3X |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)
XRT86VL3X
21
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
7.
Re-initiate the TxSOT interrupt enable.
8.
Write 0xE0 into the transmit byte count register (buffer 1).
9.
Write the next 96-bytes into 0xn700 (buffer 1, automatically incremented).
10.
Enable the LAPD transmission by writing to register 0xn113.
11.
Wait for the TxSOT before writing the next 96-bytes.
12.
Continue until the entire message is sent.
2.4
Programming Sequence for Receiving LAPD Messages
The XRT86VL3x can extract data link information from incoming DS1 frames from either the datalink bits
themselves or the D/E time slots within the PCM input data. To extract a LAPD message, the following
programming sequence can be used as a reference.
1.
Enable RxEOT in the Data Link Interrupt Enable Register.
2.
Wait for the RxEOT interrupt to occur.
3.
Once RxEOT occurs, read the Receive Data Link Byte Count Register to determine which buffer the data is
extracted to and how many bytes are contained within the message.
4.
Read the exact amount of bytes from the proper buffer. If buffer 0, read 0xn600. If buffer 1, read 0xn700. These
two registers are automatically incremented.
2.5
SS7 (Signaling System Number 7) for ESF in DS1 Only
To support SS7 specifications while receiving LAPD messages, EXAR’s Framer will generate an interrupt (if
SS7 is enabled) once the HDLC controllers have received more than 276 bytes within two flag sequences
(0x7E) of a LAPD message. Each HDLC controller supports SS7. For example: To enable SS7 for all HDLC
controllers, registers 0xnB11 (LAPD1), 0xnB19 (LAPD2), 0xnB29 (LAPD3) must be set to 0x01.
2.6
DS1/E1 Datalink Transmission Using the HDLC Controllers
The transmit framer block can insert data link information to outbound DS1/E1 frames. The data link
information can be inserted from the following sources.
Transmit Overhead Input Interface (TxOH)
Transmit HDLC1 Controller
Transmit Serial Input Interface (TxSER)
N
OTE
:
HDLC1 is the dedicated controller for transmission of LAPD messages through the datalink bits. If the datalink bits
are not used for LAPD messages, then HDLC1 can be used through the D/E time slots as with HDLC2 and HDLC3.
The Transmit Data Link Source Select bits within the Transmit Data Link Select Register (TSDLSR) determine
the source for the data link bits in ESF, SLC96, or T1DM for DS1 and CRC multi frame for E1. Each Transmit
HDLC Controller contains four major functional modules.
Bit-Oriented Signaling Processor
LAPD Controller
SLC96 Data Link Controller
Automatic Performance Report (APR) Generation
2.7
Transmit BOS (Bit Oriented Signaling) Processor
The Transmit BOS Processor handles transmission of BOS messages through the data link channel. The
processor can be set for a specific amount of repetitions a certain BOS message will be transmitted, or it may
be placed in an infinite loop. The processor can also insert a BOS IDLE flag sequence and/or an ABORT
sequence to be transmitted on the data link channel.
2.7.1
Description of BOS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。