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參數(shù)資料
| 型號(hào)： | 82C836B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 125/205頁(yè) |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836B |
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Table 10-17.
Index 62H----Fast Video RAM Enable
Bit
Description
Bit
Description
7
0BC000H - 0BFFFFH
3
0AC000H - 0AFFFFH
6
0B8000H - 0BBFFFH
2
0A8000H - 0ABFFFH
5
0B4000H - 0B7FFFH
1
0A4000H - 0A7FFFH
4
0B0000H - 0B3FFFH
0
0A0000H - 0A3FFFH
Table 10-18.
Index 63H----High Performance Refresh
Bit
Name
Description
7
Hidden Refresh
Enable
Causes system-initiated refresh cycles to be performed by inserting CPU
wait states as needed instead of using HOLD/HLDA protocol. In a
cache-based system, this allows the CPU to continue performing cache read
hit cycles simultaneously with a refresh cycle in local memory and on the
AT bus. If the CPU tries to access local memory or the AT bus while a
hidden refresh cycle is in progress, the CPU is delayed via wait states until
the refresh is completed.
0 = Normal HOLD/HLDA refresh (default)
1 = Hidden refresh
6
Refresh on
idle
This bit causes hidden refresh cycles (if enabled) to be initiated only
following a CPU Idle state (no -ADS since last -READY, and HLDA
inactive). Depending on system workloads, waiting for CPU Idle states
may slightly increase the probability of successfully hiding refresh cycles
during cache read hits.
0 = Hidden refresh doesn’t wait for CPU Idle (default)
1 = Hidden refresh waits for CPU Idle (or timeout)
If no CPU Idle states occur within the normal time limit between refresh
cycles, then refresh is initiated after the current CPU cycle terminates
(-READY), without waiting for a CPU Idle state. This insures DRAM
refresh requirements will be met even if the CPU is unusually busy.
5
AT Refresh Disable
Allows AT bus refresh to be disabled during hidden refresh. The total time
needed to perform a hidden refresh is greatly reduced in this mode, since
local memory requires far less time for a refresh than the AT bus. The result
is a significant performance benefit in cache-based systems if AT bus refresh
is not needed (non-cache systems will not benefit as much beause of the
performance effect of running exclusively in nonpipeline mode).
0 = AT refresh enabled during hidden refresh (default)
1 = AT refresh disabled during hidden (non-HLDA) refresh
-REF and -MEMR are not generated during hidden refresh if AT refresh is
disabled. However, any refreshes performed while HLDA is active for
DMA or Master cycles are still performed in the normal manner, including
refresh on the AT bus.
82C386 CHIPSet Data Sheet
Configuration Registers
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
10-13
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PDF描述 |
|---|---|
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S101BYA | 2.6GHz Relay, 1 Form C, 0.5A 30VDC Relay, 50ohms, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 82C84A_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
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