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參數(shù)資料
| 型號： | 82C836B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 49/205頁 |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836B |
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Three different types of local memory cycles can occur (listed in order of increasing
cycle time):
Page hit: -RAS is already active and the row address is already valid, so only -CAS
needs to be cycled.
RAS high: -RAS for the target bank is high initially, so there is no need to wait for
-RAS precharge time.
Page miss: Access to the same bank, but with a different row address, so -RAS must
be cycled high and low before -CAS timing can begin.
The major difference between MRA and SRA modes, and the reason for implementing
MRA mode, is the performance improvement in bank switch cycles. ‘‘Bank switch’’
means accessing a different DRAM bank than the preceding DRAM access. With MRA
mode, RAS for the new bank frequently will be already active from an earlier access, so
the bank switch can be performed without any delay for RAS cycling. The result is a
cycle equal in speed to a page hit. In contrast, SRA mode forces all bank switch cycles
to be RAS high cycles, since RAS for the new bank will always be high initially.
T-state counts for these cycles are as follows:
Page hit read is 0WS
Page hit write is 1WS
RAS high read or write, nonencoded RAS is 1WS
RAS high read or write, encoded RAS is 2WS
Page miss, same bank, read or write is 3WS
The total number of T-states for pipelined cycles is the WS amount plus 2; for
nonpipelined cycles, WS plus 3. If EMS is enabled, one further T-state is added for all
cycle types for accesses that require address translation. A minimum of 2.5 T-states are
always allowed for read data access from -RAS (100ns at 25MHz CPU speed, 125ns at
20MHz CPU speed, 156ns at 16MHz CPU speed). This allows the use of 60ns DRAMs
at 25MHz, 80ns DRAMs at 20MHz, or 100ns DRAMs at 16MHz.
The majority of all memory accesses are instruction fetches, which tend to cluster in short
bursts of accesses in highly localized address ranges. Even jump operations frequently
are localized. Thus, paging usually results in substantial performance improvement over
nonpaged memory timing, since a high percentage of memory cycles can be -CAS only.
In addition to paging, four-way page interleaving is automatically performed in Banks
0-3 whenever they all contain the same size DRAM (configurations 05H, 0EH and 13H
through 16H). Page interleaving means that the physical DRAM pages (-CAS only
adressable blocks) are interleaved in sequence across the four banks i.e., page n in Bank
0, n+1 in Bank 1, n+2 in Bank 2, n+3 in Bank 3, n+4 in Bank 0 again, and so on. This
has the effect of increasing the relative probability of bank switch cycles over page
misses; resulting in significant performance improvement over simple paging without
interleaving.
Similarly, if Banks 4-7 are enabled and contain the same size DRAMs, four-way page
interleaving is automatically performed in those four banks. Refer to configurations 12H
and 16H in Table 5-2 (shown earlier).
I
DRAM Interface
System Interface
5-8
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
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