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參數(shù)資料
| 型號(hào)： | 82C836B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 159/205頁 |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836B |
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Byte swapping remains the responsibility of the 82C836, but any bus conversion
that might be needed must be performed by the add-on card bus master. For byte
swapping purposes, the Master is treated as a 16-bit resource and must not drive the
SD0-7 and SD8-15 buses in a way that would conflict with byte swapping being
performed by the 82C836.
-SMEMR and -SMEMW remain under control of -LOMEGCS, which is driven by
the 82C836 in response to the AT Bus address generated by the Master.
While an add-on card bus master is in control, it can request a refresh cycle by driving
the -REFRESH signal low. The 82C836 will then perform a refresh cycle in the normal
manner, controlled by the 82C836.
By holding -REFRESH low longer than needed for a single refresh, the Master can
request multiple back-to-back refresh cycles.
DMA and Master Access to Local Memory
During DMA and Master cycles, (see Figure 11-13) local memory timing follows a
somewhat different protocol than during CPU cycles:
If any -RAS signal was low, it is driven high when HLDA goes high.
A0-23 flow through the 82C836 to determine the row address.
The 82C836 then waits for -XMEMR or -XMEMW to be asserted.
The memory command causes -RAS to go low immediately.
Two rising edges of PROCCLK must then occur (A, B) before row/column
changeover takes place.
One PROCCLK after that, -CAS is asserted (C). On Master writes, additional clock
cycles can be programmed between B and C (see ICR 64H).
-CAS, -RAS and column address remain valid until the end of command.
If the cycle is a memory read, -MWE is driven high at the same time that -RAS is
driven low.
Memory Refresh (HLDA and 14MHz-Based)
Figure 11-16 shows CAS-before-RAS using HOLD/HLDA protocol and the 14.3MHz
time base. It applies to either system initiated refresh or master initiated refresh while
power is good (PWRGOOD high). Refreshing ceases during power down unless standby
refresh has been enabled (see ICR 60H). Laptop applications using the 82C836 can use
standby refresh to preserve DRAM contents during power down. The basic 82C836
refresh protocol is as follows:
If a system initiated refresh immediately follows a DRAM write in early READY or
LBA mode (as depicted in Figure 11-16), CAS goes high at the middle of the first TH,
and RAS goes high at the end of the first TH. In all other cases of system initiated
refresh, HLDA causes all RAS lines to go high.
System Timing Relationships
CPU Access to AT-Bus
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
11-27
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S101BYA | 2.6GHz Relay, 1 Form C, 0.5A 30VDC Relay, 50ohms, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 82C84A_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
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