- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376472 > 82C836B (Electronic Theatre Controls, Inc.) Single-Chip 386sx AT PDF資料下載
參數(shù)資料
| 型號： | 82C836B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 40/205頁 |
| 文件大小： | 3878K |
| 代理商： | 82C836B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
must be valid near the beginning of command; and must remain valid for a short hold
time after the end of command. The command active time can be lengthened by
deasserting IOCHRDY, or (in most cases) shortened by asserting 0WS.
Master cycles on the AT bus follow the same protocol as CPU controlled cycles,
except ALE remains continuously active (high), and unlatched address timing follows
latched address timing. Address and command signals are controlled by the add-on
card bus master during Master cycles.
DMA cycles on the AT bus follow the same basic protocol as Master cycles except
the 82C836 controls the address and command signals, and commands always occur
in pairs (I/O read and memory write, or memory read and I/O write).
The minimum CPU local bus cycle in pipelined mode is two T-states, which occurs most
often on CAS-only accesses to local memory (see
Section 5, System Interface
, subsection
titled
ROM/Shadow RAM Interface
). In nonpipelined mode, the corresponding minimum
is three T-states, which the 82C836 assures by appropriately controlling the timing of
READY. If READY is controlled externally, two T-state cycles in nonpipelined mode
are possible as follows:
During coprocessor accesses in which the coprocessor generates -READYO soon
enough to end the cycle after only two T-states. This can occur only if the 82C836
has been programmed to let the coprocessor control ready during coprocessor
accesses, and if the coprocessor -READYO output has been properly interfaced to
CPU -READY as described in
Section 5, System Interface
, subsection titled
Numeric
Coprocessor Interface
.
During external cache ‘‘hit’’ memory reads, as discussed in
Section 5, System Interface
,
subsection titled
DRAM Interface, Support for External Cache
. Detailed timing
diagrams are included in
System Timing Relationships
.
The 80386sx, unlike the 80286, has the ability to keep the address valid until the Next
Address signal(NA-) is asserted. During AT bus accesses, the 82C836 takes advantage
of this feature to eliminate the need for external address latches between CPU address
and AT bus address. Less expensive transparent buffers (74F245 or equivalent) may be
used instead of latching buffers.
Address bits A20 and A0 receive special treatment in AT-compatible architectures such
as SCATsx, for the following reasons:
For compatibility with the 8088 and 8086 at address FFFF:10H and above; it is
necessary to force A20 low during CPU accesses to memory in an 80386sx or 80286
based system. The original AT-compatible approach used the GATE A20 signal from
the keyboard controller to accomplish this, but there is considerable time delay in this
approach. With the advent of the PS/2 architectures, a ‘‘Fast Gate A20’’ function was
implemented in port92H. SCATsx supports both approaches. Setting 8042 GATE
A20 high or Fast Gate A20 to one allows the modified A20 to track CPU A20 during
CPU accesses. During DMA and Master cycles, the modified A20 always tracks CPU
A20, even if modified A20 is being forced low during CPU accesses.
During conversion of 16-bit CPU accesses to paired 8-bit AT bus cycles, A0 must be
forced high during the second 8-bit cycle even though CPU A0 is still low.
Clock/Bus Control
Bus Control Arbitration and Basic Timing
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
4-5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S101BYA | 2.6GHz Relay, 1 Form C, 0.5A 30VDC Relay, 50ohms, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 82C84A_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。