- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376472 > 82C836B (Electronic Theatre Controls, Inc.) Single-Chip 386sx AT PDF資料下載
參數(shù)資料
| 型號： | 82C836B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 94/205頁 |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當(dāng)前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
Program Condition
The Program condition is entered whenever HLDA is inactive and internal select is
active. The internal select is derived from the top-level decode (described earlier).
During this time, address lines A0-A3 become inputs if DMA1 is selected, or A1-A4
become inputs if DMA2 is selected.
Note:
When DMA2 is selected, A0 is ignored.
These address inputs are used to select the DMA controller registers to be read or written.
Due to the large number of internal registers in the DMA subsystem, an internal flip-flop
is used to supplement the addressing of the count and address registers. This bit is used
to select between the high and low bytes of these registers. The flip-flop toggles each
time a read or write occurs to any of the word count or address registers in the DMA.
The internal flip-flop is cleared by a hardware RESET or a Master Clear command and
may be set or cleared by the CPU issuing the appropriate command.
Special commands are supported by the DMA subsystem in the Program condition to
control the device. These commands do not make use of the data bus, but are derived
from a set of addresses, the internal select, and -IOW or -IOR. These commands are
Master Clear, Clear Register, Clear Mode Register Counter, Set, and Clear Byte Pointer
Flip-Flop.
The 82C836 enables programming whenever HLDA has been inactive for one DMA
clock cycle. It is the responsibility of the system to ensure that programming and HLDA
are mutually exclusive. Erratic operation of the 82C836 can occur if a request for service
occurs on an unmasked channel that is being programmed. The channel should be
masked, or the DMA disabled, to prevent the 82C836 from attempting to service a device
with a channel which is partially programmed.
Active Condition
The 82C836 DMA subsystem enters the Active condition whenever a software request
occurs or a DMA request on an unmasked channel occurs, and the device is not in the
Program condition. The 82C836 then begins a DMA transfer cycle.
In an I/O-to-memory cycle, for example, after receiving a DREQ, the 82C836 asserts
HOLD to the CPU. On the next clock cycle, the DMA exits the Idle condition and enters
state S0, where it remains until HLDA is returned. After detecting HLDA, the DMA
enters state S1, during which the DMA controller generates the memory address, resolves
priority and issues DACK on the highest priority channel requesting service. The DMA
then proceeds to state S2, at which time the 82C836 asserts -XIOR. Next, the device
transitions into S3, where the -XMEMW command is asserted. This is followed by a
minimum of one DMA wait state, SW, where the 82C836 remains until the wait-state
counter has decremented to zero and IOCHRDY is true. At least one SW always occurs,
but the S3 state can be deleted if the compressed timing is selected. Once a ready
condition is detected, the DMA enters S4, where both commands are deasserted. In
I
DMA Operations
DMA Controller
8-4
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S101BYA | 2.6GHz Relay, 1 Form C, 0.5A 30VDC Relay, 50ohms, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 82C84A_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。