File: vld.fm5, modified 7/26/99
PRELIMINARY INFORMATION
14-1
Variable Length Decoder
Chapter 14
by Gene Pinkston and Selliah Rathnam
14.1
VLD OVERVIEW
The VLD block Huffman decodes MPEG1 and MPEG2
(Main Profile) video bitstreams[1-3]. This document de-
scribes a programmers view of the VLD. The VLD reads
an MPEG stream from main memory, decodes the bit-
stream under the control of DSPCPU and outputs two
data streams. The output data streams contain: 1) mac-
roblock header information and 2) the run length encod-
ed DCT coefficients. The output data streams are stored
in the main memory buffers.
The VLD unit, enabled by the DSPCPU, operates inde-
pendently during the slice decoding process. The re-
maining decoding of the MPEG stream is carried out by
the DSPCPU.
14.2
VLD OPERATION
The VLD can be initialized by the hardware or software
reset operations. The hardware reset is provided by the
external TRI_RESET# pin. The software reset is provid-
ed by one of the VLD commands. The DSPCPU controls
the VLD through the VLD command register. There are
five commands supported by the VLD:
Shift the bitstream by some number of bits (a maxi-
mum of 15-bit shift)
Search for the next start code
Reset the VLD
Parse some number of macroblocks
Flush VLD output buffers to main memory
The normal mode of operation will be for the DSPCPU to
request the VLD to parse some number of macroblocks.
Once the VLD has begun parsing macroblocks it may
stop for any one of the following reasons:
The command was completed with no exceptions
A start code was detected
An error was encountered in the bitstream
The VLD input DMA completed and the VLD is
stalled waiting for more data
HWY_BUS
RD Buffer
Macroblock
DMA
ENGINE
Control
status
MMIO &
CONF REGs
SHIFTER
start_code_
detector
mb_addr
mb_type
cbp
dmv &
motion
dct_lum
dct_chr
dctcoef
(0)
dctcoef
(1)
escape_codes
VLD
FLOW
Control
Interrupt
Run-Level
Hdr WR FIFO
WR FIFO
Figure 14-1. VLD Block Diagram
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