TM1100 Preliminary Data Book
Philips Semiconductors
20-2
PRELIMINARY INFORMATION
File: power.fm5, modified 7/23/99
use a separate function with the address of the variable
as a parameter and this function needs to be compiled
specifically without interruptible jumps.
The wake-up from power down mode takes approxi-
mately 20 SDRAM clock cycles. This amount of time is
added to the worst case latency for memory requests
compared to the situation when the system is not in pow-
er down mode.
20.5
DETAILED SEQUENCE OF EVENTS
The sequence of events to power down TM1100 is as fol-
lows:
Issue a MMIO write to the POWER_DOWN register
The main memory interface waits till the completion
of the current main memory transfer, if there is one
still busy.
The MMI brings SDRAM into the self refresh state,
goes into a wait state and asserts the global signal
global_power_down.
All units that participate in the power down, respond
to the global_power_down signal by disabling their
clocks.
Only the PLL, interrupt controller, timers, wake-up
logic, the PCI bus interface and any peripherals, that
have their SLEEPLESS bit control bit set, continue to
be clocked. Also the SDRAM clock continues.
An interrupt is detected by the interrupt controller or a
unit that didn’t participate in the power down
requests a memory transfer.
The MMI deasserts the global_power_down signal,
activating all blocks on the chip.
The MMI recovers SDRAM from self-refresh.
The MMI causes completion of the MMIO operation
that initiated the power down sequence.
When software takes an interruptible branch opera-
tion, the interrupt that caused the wake_up will be
serviced (if the wake-up was initiated by an interrupt).
20.6
MMIO REGISTER POWER_DOWN
The register POWER_DOWN has an offset 0x100108 in
the MMIO aperture.
The register POWER_DOWN is without content. Writing
to this register has the side-effect to power down the
chip. Reading from this register returns an undefined val-
ue and has no side-effect.