Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-27
Dual clipped subtract of signed 16-bit halfwords
SYNTAX
[ IF r
guard ] dspidualsub rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then {
temp1
← sign_ext16to32(rsrc1<15:0>) – sign_ext16to32(rsrc2<15:0>)
temp2
← sign_ext16to32(rsrc1<31:16>) – sign_ext16to32(rsrc2<31:16>)
if temp1 < 0xffff8000 then temp1
← 0x8000
if temp2 < 0xffff8000 then temp2
← 0x8000
if temp1 > 0x7fff then temp1
← 0x7fff
if temp2 > 0x7fff then temp2
← 0x7fff
r
dest<31:16>
← temp2<15:0>
r
dest<15:0>
← temp1<15:0>
}
ATTRIBUTES
Function unit
dspalu
Operation code
71
Number of operands
2
Modier
No
Modier range
—
Latency
2
Issue slots
1, 3
DESCRIPTION
As shown below, the dspidualsub operation computes two 16-bit clipped, signed differences separately on the
two pairs of high and low 16-bit halfwords of r
src1 and rsrc2. Both differences are clipped into the range [215–1..–215]
(or [0x7fff..0x8000]) and written into the corresponding halfwords of r
dest. All values are signed 16-bit integers.
The dspidualsub operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls
the modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x12340032, r40 = 0x00010002
dspidualsub r30 r40
→ r60
r60
← 0x12330030
r10 = 0, r30 = 0x12340032, r40 = 0x00010002
IF r10 dspidualsub r30 r40
→ r70
no change, since guard is
false
r20 = 1, r30 = 0x12340032, r40 = 0x00010002
IF r20 dspidualsub r30 r40
→ r100 r100 ← 0x12330030
r50 = 0x80000001, r80 = 0x00018001
dspidualsub r50 r80
→ r90
r90
← 0x80007fff
r110 = 0x00018001, r120 = 0x80010002
dspidualsub r110 r120
→ r125
r125
← 0x7fff8000
0
1
3
r
src1
0
1
3
r
src2
0
3
r
dest
1
0
1
0
1
Two full-precision
17-bit signed differences
Clip to [215–1..–215]
signed
SEE ALSO
dspidualsub