Philips Semiconductors
DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99
PRELIMINARY INFORMATION
A-59
Floating-point square root
SYNTAX
[ IF r
guard ] fsqrt rsrc1
→ rdest
FUNCTION
if r
guard then
r
dest
← square_root(rsrc1)
ATTRIBUTES
Function unit
ftough
Operation code
110
Number of operands
1
Modier
No
Modier range
—
Latency
17
Recovery
16
Issue slots
2
DESCRIPTION
The fsqrt operation computes the squareroot of r
src1 and stores the result into rdest. All values are in IEEE
single-precision oating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument
is denormalized, zero is substituted for the argument before computing the squareroot, and the IFZ ag in the PCSW
is set. If the result is denormalized, the result is set to zero instead, and the OFZ ag in the PCSW is set. If fsqrt
causes an IEEE exception, the corresponding exception ags in the PCSW are set. The PCSW exception ags are
sticky: the ags can be set as a side-effect of any oating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the PCSW exception ags occurs at the same time as r
dest is written. If any
other oating-point compute operations update the PCSW at the same time, the net result in each exception ag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception ag.
The fsqrtflags operation computes the exception ags that would result from an individual fsqrt.
The fsqrt operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest and the exception ags in PCSW are written;
otherwise, r
dest is not changed and the operation does not affect the exception ags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0)
fsqrt r60
→ r90
r90
← 0xffffffff (QNaN), INV ag set
r40 = 0x40400000 (3.0)
fsqrt r40
→ r95
r95
← 0x3fddb3d7 (1.732051), INX ag set
r10 = 0, r40 = 0x40400000 (3.0)
IF r10 fsqrt r40
→ r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0)
IF r20 fsqrt r40
→ r110 r110 ← 0x3fddb3d7 (1.732051), INX ag set
r82 = 0x00c00000 (1.763241526e–38) fsqrt r82
→ r112
r112
← 0x201cc471 (1.32787105e-19), INX ag set
r84 = 0x7f800000 (+INF)
fsqrt r84
→ r113
r113
← 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
fsqrt r70
→ r120
r120
← 0x5f7fffff (1.8446743e19), INX ag set
r80 = 0x00400000 (5.877471754e-39)
fsqrt r80
→ r125
r125
← 0, IFZ ag set
SEE ALSO
fsqrt