TM1100 Preliminary Data Book
Philips Semiconductors
7-20
PRELIMINARY INFORMATION
File: evo.fm5, modified 7/24/99
ppm. When using a Philips DENC (Digital Encoder), the
color burst frequency is derived from the master DENC
frequency by a programmable synthesizer on the DENC
chip. In this case, VO_CLK changes larger than 50 ppm
are allowed by changing the DENC synthesizer over I2C
to compensate for the VO_CLK change.
7.16
NEW FEATURES OF TM1100
The remainder of this document contains the specifica-
tions of the Enhanced Video Out unit (EVO) for the
TM1100 processor. The EVO is fully functional and bina-
ry compatible with the Video Out unit of TM1000.
7.17
BACKWARD COMPATIBILITY
The Enhanced Video Out unit (called EVO in the rest of
this document) is fully compatible with the current Video
Out unit. All features of TM1000 VO are supported exact-
ly in the same fashion in EVO. A code controlling
TM1000 VO identically controls the EVO.
All the new features are controlled through new MMIO
registers, and the EVO_ENABLE (Enhanced Video Out
Enable) bit in the new EVO_CTL MMIO register switches
on (EVO_ENABLE=1) or off the new features.
7.18
SUMMARY OF NEW EVO FEATURES
The new EVO will have the following features that are not
present in the previous versions of TM1000:
1. Full 129-level alpha blending (8-bit alpha value).
2. Chroma-key: A particular register (in YUV4:2:2+a) is
used as the key that signies full transparency for the
overlay.
3. Genlock mode frame synchronization by an external
signal on VO_IO2).
4. The frame synchronization signal on VO_IO2 is mod-
ied to follow the eld number generated in the EAV/
SAV code
5. The YUV output value can be clipped at programma-
ble values.
6. In data streaming mode, a Data valid signal is gener-
ated on VO_IO2.
7. The message passing mode can support short mes-
sages (1 word). VO_IO2 (ENDMSG) only toggles
when it is necessary.
7.19
CONTROLS: MMIO REGISTERS
New features of EVO are controlled by setting the appro-
priate flags in the EVO_CTL MMIO register.
After reset, all bits of all registers of EVO are set to “0”,
except for the CLIPPING register which is initialized to
0xF010EB10 and the EVO_CTL register which is set to
0x10000000.
The register fields are described in the
Table 7-11 and
Table 7-12. To ensure compatibility with future devices,
any undefined MMIO bits should be ignored when read,
and written as zeroes.
Table 7-10. DDS and PLL example settings
Desired
Frequency
DDS frequency
PLL_S
PLL_T
CLOCK_SELECT
Usage
4 - 10 MHz
8 - 20 MHz
1 (divide by 2)
01 (T divider)
custom low speed video
8 - 45 MHz
1 (divide by 2)
00 (VCO)
standard or 16:9 digital video
40 - 80 MHz
20 - 40 MHz
1 (divide by 2)
3 (divide by 4)
00 (VCO)
high pixel rate custom video