參數(shù)資料
型號(hào): 935262469557
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP240
封裝: 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240
文件頁(yè)數(shù): 19/518頁(yè)
文件大?。?/td> 7111K
代理商: 935262469557
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Philips Semiconductors
Video Out
File: evo.fm5, modified 7/24/99
PRELIMINARY INFORMATION
7-13
7.13.1
Status Register
The VO_STATUS register is a read-only register that shows the current status of the VO. Its fields are shown in
7.13.2
Control Register
The VO_CTL register sets the operating mode, interrupt enables and clears interrupt flags and initiates VO operations.
Its fields are shown in Table 7-7.
Table 7-6. Status Register Fields
Field
Description
CUR_Y
Current Y: image line index of the current line in the current eld being output by VO. CUR_Y reects current state of
the Image Line Counter. CUR_X & CUR_Y form a single 24-bit output data byte counter (CUR_X=counter LSBs)
when VO in data-streaming or message-passing mode. This counter reects the status of the SIZE counter for the
currently active buffer. The two LSBs of this counter are not valid for reading during transfers; only the upper 22 bits
(the word count) are valid.
CUR_X
Current X: image pixel index of the most-recently output pixel. CUR_X reects the current state of the Image Pixel
Counter.
BFR1_EMPTY
BFR2_EMPTY
Buffers 1 & 2 Empty: these bits are valid in video refresh, data-streaming & message-passing modes.
In video refresh modes, only buffer 1 is used. BFR1_EMPTY indicates that the last byte of a eld has been trans-
ferred. It is actually raised at the completion of the transmission of the Overlap area of the eld, as per
Figure 7-26. At this point, software should assign a new eld of imagery to Y,U,V_BASE_ADR and perform a
BFR1_ACK. If BFR1_EMPTY is not cleared by BFR1_ACK before the start of emission of the active video area of
the next eld, the VO sets the URUN bit.
In data-streaming mode, BFR1_EMPTY and BFR2_EMPTY indicate that the last byte in their corresponding
buffer has been transferred. When BFR1_EMPTY or BFR2_EMPTY is set, transfer stops from the corresponding
buffer.
In message passing mode, BFR1_EMPTY signals completion of message transmission.
These bits cause an interrupt if their interrupts enables are set, and one interrupt per buffer is signaled.
HBE
Highway Bandwidth Error: HBE is set when the SDRAM highway fails to respond in time to a highway read request
and data was not ready in time to be set on VO data lines. HBE can be set in both image- and data-transfer modes.
HBE indicates insufcient bandwidth was requested from the highway arbiter.
YTR
In video refresh modes, YTR indicates that the Image Line Counter value is equal to the Y THRESHOLD value in
VO_YTHR. The Y THRESHOLD value can be set to provide an interrupt on any line in the valid image area.
URUN
Underrun: in video refresh and data-streaming modes, this bit indicates that the CPU did not perform an acknowl-
edge to indicate updated address pointers for the next eld or buffer in time for continuous image or data transfer.
URUN causes an interrupt if corresponding enable set.
In video refresh modes, URUN indicates the SAV code marking beginning of active video has been generated
without BFR1_ACK resetting BFR1_EMPTY. In this case, video refresh continues with previous address pointers.
In data-streaming mode, URUN indicates the last byte in active buffer was transferred, and no BFR1_ACK or
BFR2_ACK occurred to enable next buffer. In this case, transfer continues with previous address pointers.
FIELD2
Field 2/Bfr 2 Active: in data streaming modes, zero when buffer 1 is active; one when buffer 2 is active.
In video refresh modes, FIELD2 indicates that VO is actively sending out a video image for eld 2, as dened by
VBLANK
Vertical Blanking: indicates VO is in a vertical-blanking interval. VBLANK active only in video refresh modes.
Table 7-7. VO_CTL Register Fields
Field
Description
RESET
Software reset of VO. The recommended software reset procedure is:
1. Write desired VO_CTL state with RESET bit set, VO_ENABLE clear.
2. Write desired VO_CTL state with RESET bit clear, VO_ENABLE clear.
3. Wait at least 5 VO-clocks.
4. Write desired VO_CTL with RESET bit clear, VO_ENABLE set.
Note:
A hardware reset clears CLKOUT & SYNC_MASTER bits and put VO_CLK, VO_IO1, & VO_IO2 in input state.
This results in a VO_CTL value of 32400000h.
In contrast a software reset does not change device registers. So software reset results in a state as specied by
the VO_CTL word value written during the above procedure.
SLEEPLESS
Prevents power down of the VO when TM1100 power down is active.
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