
Philips Semiconductors
Overview
File: intro.fm5, modified 7/23/99
PRELIMINARY INFORMATION
2-3
trol state of a TM1100 in a target system. It also imple-
ments 1149.1 boundary scan functionality.
2.4
BRIEF EXAMPLES OF OPERATION
The key to understanding TM1100 operation is observ-
ing that the DSPCPU and peripherals are time-shared
and that communication between units is through
SDRAM memory. The DSPCPU switches from one task
to the next; first it decompresses a video frame, then it
decompresses a slice of the audio stream, then back to
video, etc. As necessary, the DSPCPU issues com-
mands to the peripheral function units to orchestrate their
operation.
The DSPCPU can enlist the ICP and other co-proces-
sors to help with some of the straightforward, tedious
tasks associated with video processing. The ICP is very
well suited for arbitrary size horizontal and vertical video
resizing and color space conversion.
The DSPCPU can enlist the input/output peripherals to
autonomously receive or transmit digital video and audio
data with minimal CPU supervision. The I/O units have
been designed to interface to the outside world through
industry standard audio and video interfaces, while deliv-
ering or taking data in memory in formats suitable for
software processing.
2.4.1
Video Decompression in a PC
An example of operation for a TM1100 system is to serve
as a video-decompression engine on a PCI card in a PC.
In this case, the PC doesn’t need to know the TM1100
has a powerful, general-purpose CPU; rather, the PC
just treats the hardware on the PCI card as a “black-box”
engine.
Video decompression begins when the PC operating
system hands the TM1100 a pointer to compressed vid-
eo data in the PC’s memory (the details of the communi-
cation protocol are handled by the software driver in-
stalled in the PC’s operating system).
The DSPCPU fetches data from the compressed video
stream via the PCI bus, decompresses frames from the
video stream, and places them into local SDRAM. De-
compression may be aided by the VLD (variable-length
decoder) co-processor unit, which implements Huffman
decoding and is controlled by the DSPCPU.
When a frame is ready for display, the DSPCPU gives
the ICP (image coprocessor) a display command. The
ICP then autonomously fetches the decompressed
frame data from SDRAM and transfers it over the PCI
bus to the frame buffer in the PC’s video display card. Al-
ternately, video can be sent to the graphics card using
the CCIR656 video output.
2.4.2
Video Compression
Another typical application for TM1100 is in video com-
pression. In this case, uncompressed video is usually
supplied directly to the TM1100 system via the video-in
unit. A camera chip connected directly to the video-in unit
supplies YUV data in eight-bit, 4:2:2 format. The video-in
unit takes care of sampling the data from the camera
chip and demultiplexing the raw video to SDRAM in three
separate areas, one each for Y, U, and V.
When a complete video frame has been read from the
camera chip by the video-in unit, it interrupts the
DSPCPU. The DSPCPU compresses the video data in
software (using a set of powerful data-parallel multime-
dia operations) and writes the compressed data to a sep-
arate area of SDRAM.
The compressed video data can now be transmitted or
stored in any of several ways. It can be sent to a host
system over the PCI bus for archival on local mass stor-
age, or the host can transfer the compressed video over
a network. The data can also be sent to a remote system
using the modem/ISDN interface to create, for example,
a video phone or video conferencing system.
Since the powerful, general-purpose DSPCPU is avail-
able, the compressed data can be encrypted before be-
ing transferred for security.
2.5
INTRODUCTION TO TM1100 BLOCKS
The remainder of this chapter provides a brief introduc-
tion to the internal components of TM1100.
2.5.1
Internal “Data Highway” Bus
The internal data bus connects all internal blocks togeth-
er and provides access to internal control/status regis-
ters of each block, external SDRAM, and the external
bus peripheral chips. The internal bus consists of sepa-
rate 32-bit data and address buses, and transactions on
the bus use a block-transfer protocol. On-chip peripheral
units and co-processors can be masters or slaves on the
bus.
Access to the internal bus is controlled by a central arbi-
ter, which has a request line from each potential bus
master. The arbiter is programmable to provide guaran-
teed bandwidth and latency to requestors so that the ar-
bitration algorithm can be tailored for different applica-
tions. Peripheral units make requests to the arbiter for
bus access, and depending on the arbitration mode, bus
bandwidth is allocated to the units in different amounts.
Each mode allocates bandwidth differently, but each
mode guarantees each unit a minimum bandwidth and
maximum service latency. All unused bandwidth is allo-
cated to the DSPCPU.
The bus allocation mechanism is one of the features of
TM1100 that makes it a true real-time system instead of
just a highly integrated microprocessor with unusual pe-
ripherals.
2.5.2
VLIW Processor Core
The heart of TM1100 is its powerful 32-bit DSPCPU
core. The DSPCPU implements a 32-bit linear address
space and 128, fully general-purpose 32-bit registers.
The registers are not separated into banks; any opera-
tion can use any register for any operand.