File: mmio.fm5, modified 7/23/99
PRELIMINARY INFORMATION
B-1
MMIO Register Summary
Chapter B
by Gert Slavenburg, and Selliah Rathnam
B.1
MMIO REGISTERS
The following table lists all the MMIO registers implemented in TM1100. The registers are grouped according to the
unit to which they belong. For compatibility with future devices, any undefined MMIO bits should be ignored when read,
and written as zeroes.
MMIO Register Name
Offset
(in hex)
Accessibility
Description
DSPCPU
External
PCI
Initiators
DSPCPU Registers
DRAM_BASE
10 0000
R/W
Start of DRAM address aperture
DRAM_LIMIT
10 0004
R/W
End of DRAM address aperture
MMIO_BASE
10 0400
R/W
Start of 2-MB MMIO-register address aperture
EXCVEC
10 0800
R/W
Interrupt vector (handler start address) for exceptions
ISETTING0
10 0810
R/W
Interrupt mode & priority settings for sources 0-7
ISETTING1
10 0814
R/W
Interrupt mode & priority settings for sources 8-15
ISETTING2
10 0818
R/W
Interrupt mode & priority settings for sources 16-23
ISETTING3
10 081c
R/W
Interrupt mode & priority settings for sources 24-31
IPENDING
10 0820
R/W
Interrupt-pending status bit for all 32 sources
ICLEAR
10 0824
R/W
Interrupt-clear bit for all 32 sources
IMASK
10 0828
R/W
Interrupt-mask bit for all 32 sources
INTVEC0
10 0880
R/W
Interrupt vector (handler start address) for source 0
INTVEC1
10 0884
R/W
Interrupt vector (handler start address) for source 1
INTVEC2
10 0888
R/W
Interrupt vector (handler start address) for source 2
INTVEC3
10 088c
R/W
Interrupt vector (handler start address) for source 3
INTVEC4
10 0890
R/W
Interrupt vector (handler start address) for source 4
INTVEC5
10 0894
R/W
Interrupt vector (handler start address) for source 5
INTVEC6
10 0898
R/W
Interrupt vector (handler start address) for source 6
INTVEC7
10 089c
R/W
Interrupt vector (handler start address) for source 7
INTVEC8
10 08a0
R/W
Interrupt vector (handler start address) for source 8
INTVEC9
10 08a4
R/W
Interrupt vector (handler start address) for source 9
INTVEC10
10 08a8
R/W
Interrupt vector (handler start address) for source 10
INTVEC11
10 08ac
R/W
Interrupt vector (handler start address) for source 11
INTVEC12
10 08b0
R/W
Interrupt vector (handler start address) for source 12
INTVEC13
10 08b4
R/W
Interrupt vector (handler start address) for source 13
INTVEC14
10 08b8
R/W
Interrupt vector (handler start address) for source 14
INTVEC15
10 08bc
R/W
Interrupt vector (handler start address) for source 15
INTVEC16
10 08c0
R/W
Interrupt vector (handler start address) for source 16
INTVEC17
10 08c4
R/W
Interrupt vector (handler start address) for source 17
INTVEC18
10 08c8
R/W
Interrupt vector (handler start address) for source 18
INTVEC19
10 08cc
R/W
Interrupt vector (handler start address) for source 19