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參數(shù)資料
| 型號(hào)： | DS34T102GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 14/366頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 484TEBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | TDM（分時(shí)復(fù)用） |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 484-HSBGA（23x23） |
| 包裝： | 托盤 |
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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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For example, if the desired configuration is to transmit channels 2-16 and 18-26 from the 2.048MHz TSER data
stream, the TBCS registers should be programmed as follows:
TBCS1 = 0x01 :: ignore TSER channel 1 ::
TBCS2 = 0x00
TBCS3 = 0x01 :: ignore TSER channel 17 ::
TBCS4 = 0xFC :: ignore TSER channels 27-32 ::
10.10.3.2 Mapping T1 Channels Into a 2.048MHz TDM Stream
The receive elastic store operates with a 2.048MHz system-side data rate (32 timeslots/frame) when the
RIOCR.RSCLKM bit is set to 1. In this mode, CPU software can specify which of the channels of the received T1
signal come out of the framer on RSER by programming the receive blank channel select registers (RBCS). When
a bit in these registers is set to one, RSER is forced high during the bits of that channel. Typically, CPU software
configures eight channels to be blanked (i.e. filled with all-ones) with the other 24 channels carrying the data from
the received T1 signal. The default (power-up) configuration blanks channels 25 to 32, so that the 24 T1 channels
are mapped into the first 24 channels of the 2.048MHz RSER signal. If the system blanks channel 1 (timeslot 0) by
setting RBCS1.CH1 = 1, then the F-bit from the framer is passed into the MSb of channel 1 of the RSER signal.
For example, if:
RBCS1 = 0x01
RBCS2 = 0x00
RBCS3 = 0x01
RBCS4 = 0xFC
Then on RSER:
channel 1 (MSb) = F-bit
channel 1 (bits 1-7) = all ones
channels 2-16 = T1 channels 1-15
channel 17 = all ones
channels 18-26 = T1 channels 16-24
channels 27-32 = all ones
Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit
(RESCR.RSZS) should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29)
then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications.
10.10.3.3 Sourcing E1 Channels from a 1.544MHz TDM Stream
The transmit elastic store operates with a 1.544MHz system-side data rate (24 channels / frame + F-bit) when the
TIOCR.TSCLKM bit is set to 0. In this mode CPU software can specify which of the channels of the E1 signal are
sourced from TSER and which are blanked (i.e. filled with all-ones) by programming the transmit blank channel
select registers (TBCS). When a bit in these registers is set to one, the elastic store ignores TSER data for that
channel. Typically, out of 32 total channels in the E1 signal being generated by the transmit formatter, CPU
software configures eight channels to be blanked, and 24 channels to receive the 24 channels in the TSER signal.
The default (power-up) configuration is to blank channels 25 to 32, so that so that the 24 TSER channels are
mapped into the first 24 channels of the E1 data stream.
10.10.3.4 Mapping E1 Channels Into a 1.544MHz TDM Stream
The receive elastic store operates with a 1.544MHz system-side data rate (24 channels / frame + F-bit) when the
RIOCR.RSCLKM bit is set to 0. In this mode, CPU software can specify which of the channels of the received E1
signal come out of the framer on RSER by programming the receive blank channel select registers (RBCS). When
a bit in these registers is set to one, RSER is forced high during the bits of that channel. Typically, CPU software
configures eight channels to be ignored and 24 channels to come out in the RSER signal. The default (power-up)
configuration ignores channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the
1.544MHz RSER signal. In this mode, the F-bit location at RSER is always set to 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34T102GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual TDM Over Packet Chip RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS34T104 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T104GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad TDM Over Packet Chip RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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