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參數(shù)資料
| 型號(hào)： | DS34T102GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 25/366頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 484TEBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | TDM（分時(shí)復(fù)用） |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 484-HSBGA（23x23） |
| 包裝： | 托盤 |
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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
120 of 366
in RIM7-T1. The CPU has 2ms (8 * 2 * 125
s) to read the data from RFDL before it is lost. Note that in this mode,
no zero stuffing is applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL
messaging applications.
In the SF framing mode, the framer writes the received Fs framing pattern into the lower six bits of the RFDL
register, and RLS7-T1.RFDLF is set every 1.5ms (12 * 125
s).
10.11.5 E1 Datalink
The registers related to E1 datalink are shown in the following table:
Register Name
Description
Functions
Page
Receive Align Frame Register
Rx first byte of the align frame: Si, FAS
Receive Non-Align Frame Register
Rx first byte of the non-align frame
Receive Si Bits of the Align Frames
Rx align-frame Si bits
Receive Si Bits of the Non-Align Frames
Rx non-align-frame Si bits
Receive Sa Bits
Rx Sa4-Sa8 bits
Sa Bit Interrupt Mask Register
interrupt masks for Sa bit changes
2
Received Sa Bits
last received Sa bit values
Received Sa6 Codeword
last validated Sa6 codeword
Transmit Align Frame Register
Tx first byte of the align frame: Si, FAS
Transmit Non-Align Frame Register
Tx first byte of the non-align frame
Transmit Si Bits of the Align Frame
Tx align-frame Si bits
Transmit Si Bits of the Non-Align Frames
Tx non-align-frame Si bits
Transmit Sa4 to Sa8
Tx Sa4-Sa8 bits
Transmit Sa Bit Control Register
Tx source control bits for Si, RA, SaX
The framer, when operated in the E1 mode, provides two methods for accessing the Sa and the Si bits, which are
the two common channels over which a datalink can be run. The first method involves writing/reading data every
E1 double-frame (250
s) while the second one involves writing/reading data every CRC-4 multiframe (2ms).
10.11.5.1 Per Double-Frame Access (Method 1)
On the receive side, the RAF and RNAF registers always report the contents of the first eight bits of the align frame
and the non-align frame, respectively, which includes the Si and Sa bits Both registers are updated at the start of
the align frame, which is indicated by the RLS2-E1.RAF status bit. After RAF is set to 1, software has 250
s to
read the registers before they are overwritten by the bits from the next double-frame.
On the transmit side, the TAF and TNAF registers can source the first eight bits of the align frame and the non-
align frame, respectively. Data is sampled from these registers at the start of the align frame, which is indicated by
the TLS1.TAF status bit. After TAF is set to 1, software has 250
s to update the registers with new values (if
needed) before they are sampled again for the next double-frame. TAF and TNAF are the default sources for the
FAS, Si, RAI and Sa bits. However, various control fields can cause some of these bits to be sourced from
elsewhere.
10.11.5.2 Per CRC-4 Multiframe Access (Method 2)
On the receive side, the eight registers RSiAF, RSiNAF, RRA, and RSa4 through RSa8 report the corresponding
overhead bits of the CRC-4 multiframe as they are received. These registers are updated at the start of the next
CRC-4 multiframe, which is indicated by the RLS2-E1.RCMF status bit. After RCMF is set to 1, software has 2ms
to read the registers before they are overwritten by the bits from the next multiframe.
corresponding overhead bits of the multiframe. The control bits in the TSACR register enable the sourcing of
Si/RAI/Sa bits from these registers. Data is sampled from these registers at the start of the multiframe, which is
indicated by the TLS1.TMF status bit. After TMF is set to 1, software has 2ms to update the registers (if needed)
before they are sampled again for the next multiframe.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34T102GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual TDM Over Packet Chip RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS34T104 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T104GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad TDM Over Packet Chip RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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