- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1916 > DS34T102GN+ (Maxim Integrated Products)IC TDM OVER PACKET 484TEBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS34T102GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 21/366頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 484TEBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | TDM（分時(shí)復(fù)用） |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 484-HSBGA（23x23） |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)第323頁(yè)第324頁(yè)第325頁(yè)第326頁(yè)第327頁(yè)第328頁(yè)第329頁(yè)第330頁(yè)第331頁(yè)第332頁(yè)第333頁(yè)第334頁(yè)第335頁(yè)第336頁(yè)第337頁(yè)第338頁(yè)第339頁(yè)第340頁(yè)第341頁(yè)第342頁(yè)第343頁(yè)第344頁(yè)第345頁(yè)第346頁(yè)第347頁(yè)第348頁(yè)第349頁(yè)第350頁(yè)第351頁(yè)第352頁(yè)第353頁(yè)第354頁(yè)第355頁(yè)第356頁(yè)第357頁(yè)第358頁(yè)第359頁(yè)第360頁(yè)第361頁(yè)第362頁(yè)第363頁(yè)第364頁(yè)第365頁(yè)第366頁(yè)
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
117 of 366
10.11.3.1.2 Hardware Signaling
In the hardware signaling method, signaling data is provided to the transmit formatter using the TSIG input. The
signaling information on TSIG is buffered and inserted into the outgoing framed T1 or E1 signal. In both T1 and E1
modes, signaling data can be sourced from TSIG on a per-channel basis by using the THSCS registers. Note that
in E1 mode the THSCS control bits are ignored unless TCR1-E1.T16S=0.
The signaling insertion capabilities of the transmit formatter are available whether the transmit side elastic store is
enabled or disabled. If the elastic store is enabled, the system TDM interface clock (TSYSCLK) can be either
1.544MHz or 2.048MHz. See Figure 10-33 to Figure 10-35 for functional timing of TSIG.
10.11.3.2 Receive Signaling Operation
There are two methods for the receive framer to present received signaling data to the system: software (i.e.
through the RS registers) and hardware (i.e. on the framer’s RSIG output). Both methods may be used
simultaneously. The methods are described in the subsections below.
10.11.3.2.1 Software Signaling
In the software signaling method, the framer extracts signaling information from the receive data stream and copies
it into the receive signaling registers (RS1 through RS16) where it can be read by the CPU. The signaling
information in these registers is always updated on multiframe boundaries. The CPU can watch for the setting of
the RLS4.RMF latched status bit on multiframe boundaries to know when to read the signaling information. This
function is always enabled.
10.11.3.2.2 Change Of State Indication
To free the CPU from the task of continually monitoring the receive signaling registers, the framer can be
programmed to alert the system when any channel(s) have a change of signaling state. When a channel’s signaling
data changes state, the latched status bit for that channel is set to 1 in the RSS registers. If the corresponding bit in
the RSCSE registers is set, then the setting of an RSS register bit causes RLS4.RSCOS to also be set. RSCOS
can cause an interrupt request if enabled by the corresponding interrupt enable bit in RIM4. Note that signaling
If signaling integration is enabled (RSIGC.RSIE=1) then any new signaling state must be constant for 3
consecutive multiframes before a change of state is indicated in the RSS registers. The signaling integration mode
affects all channels in the T1 or E1 signal; it cannot be enabled/disabled on a per-channel basis.
With the functionality described above, the CPU can poll RLS4.RSCOS or respond to an interrupt request driven by
RSCOS. When RSCOS is found to be high, software can identity which channels have undergone a signaling
change of state by reading the RSS registers. Software can then read the corresponding RS1 through RS16
registers to get the new signaling state(s).
10.11.3.2.3 Hardware-Based Receive Signaling
In the hardware signaling method, the framer provides signaling data in two places: on the dedicated RSIG output
and at the normal position in the receive data stream on the RSER output. A signaling buffer in the framer provides
signaling data to RSIG and additionally allows signaling data to be reinserted into the original data stream in a
different alignment that is determined by a multiframe signal from the RSYNC input. In this mode, the receive
elastic store may be enabled or disabled. If the receive elastic store is enabled, then the system TDM interface
clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are
output on RSIG in the RCLK cycles when the lower nibble of each channel is output on RSER. The RSIG data is
updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 SF, 2ms for E1 CAS) unless a signaling freeze is in
effect (see section 10.11.3.2.6). In the SF framing mode, the AB signaling bits are output twice on RSIG in the in
the RCLK cycles when the lower nibble of each channel is output on RSER. Hence, bits 5 and 6 contain the same
data as bits 7 and 8, respectively, in each channel. These function are always enabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3501U+H | IC POT NV 128POS HV 10-USOP |
| DS3502U+ | IC POT DGTL NV 128TAP 10-MSOP |
| DS3503U+ | IC POT DGTL NV 128TAP 10-MSOP |
| DS3897MX | IC TXRX BTL TRAPEZIODAL 20-SOIC |
| DS3901E+ | IC RESIST VAR TRPL 14TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34T102GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual TDM Over Packet Chip RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS34T104 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T104GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad TDM Over Packet Chip RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。