____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
288 of 366
Register Name:
TCR2-T1
Register Description:
Transmit Control Register 2 (T1 Mode)
Register Address:
base address + 0x608
Bit #
7
6
5
4
3
2
1
0
Name
TFDLS
TSLC96
TDDSEN
FBCT2
FBCT1
TD4RM
PDE
TB7ZS
Default
0
Bit 7: TFDL Register Select (TFDLS).
0 = Source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (if TCR2-T1. TSLC96=1)
1 = Reserved
Bit 6: Transmit SLC–96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the
SLC-96 alignment pattern and data from the
TSLC registers. See section
10.11.16.0 = SLC–96 insertion disabled
1 = SLC–96 insertion enabled
Bit 5: Transmit DDS Zero Suppression Enable (TDDSEN). When set to 1, this bit enables the transmit DDS zero
suppression function to operate for the channels specified by the
TDDS registers.
0 = Disabled
1 = Enabled
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit to one enables the corruption of one out of every 128 Ft
bits (SF framing mode) or one out of every 128 FPS bits (ESF framing mode). F-bit corruption continues as long as
FBCT2=1.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A zero-to-one transition causes the next three consecutive Ft bits (SF
framing mode) or FPS bits (ESF framing mode) to be corrupted. This corruption is sufficient to cause the remote
end to experience a loss of frame synchronization.
Bit 2: Transmit D4 RAI Select (TD4RM). When the transmit formatter is in superframe mode this bit specifies the
type of RAI signal to transmit.
0 = Zeros in bit 2 of all channels (normal T1 operation)
1 = A one in the Fs bit position of frame 12 (J1 operation)
Bit 1: Pulse Density Enforcer Enable (TPDE). The framer always examines both the transmit and receive data
streams for violations of the ANSI T1.403 pulse density rules: no more than 15 consecutive zeros and at least N
ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the transmit and
receive data streams are reported in the
TLS1.TPDV and
RLS2-T1.RPDV bits respectively. When this bit is set to
one, the transmit formatter forces the transmitted stream to meet this requirement no matter the content of the
transmitted stream. When B8ZS encoding is enabled
(TCR1-T1.TB8ZS=1), this bit should be set to zero since
B8ZS-encoded data streams cannot violate the pulse density requirements.
0 = Disable transmit pulse density enforcer
1 = Enable transmit pulse density enforcer
Bit 0: Transmit Side Bit 7 Zero Suppression Enable (TB7ZS).
0 = No stuffing occurs
1 = Force bit 7 to a one as specified by
TCR1-T1.GB7S.