1045
SAM4CP [DATASHEET]
43051E–ATPL–08/14
45.7.4.2 Test Setup 2: CoreMark
CoreMark on Core 1 (CM4P1) running out of SRAM1 (Code) / SRAM2 (Data).
Core 0 (CM4P0) in Sleep Mode.
45.7.4.3 Test Setup 3: CoreMark
CoreMark on Core 0 (CM4P0) running out of Flash in 128-bit or 64-bit access mode with and without Cache
Enabled. Cache is enabled above 0 WS.
CoreMark on Core 1 (CM4P1) running out of SRAM1 (Code) / SRAM2 (Data).
Table 45-49. Test Setup 2 Current Consumption
Clock (MHz)
SRAM1, SRAM2
Unit
IDD_IN (AMP1)
22.3
19
16
12.2
9.2
7.15
5.4
2.1
1.5
0.8
0.5
0.32
0.21
0.13
IDD_I0 (AMP2)
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
IDD_CORE (AMP3)
19
16
13.83
10.66
7.9
5.5
4.15
2
1.4
0.75
0.45
0.38
0.2
0.12
120
100
84
64
48
32
24
12
8
4
2
1
0.5
0.25
mA
Table 45-50. Test Setup 3 Current Consumption
128-bit Flash Access
64-bit Flash Access
Unit
Clock
(MHz)
120
100
84
64
48
32
24
12
8
4
2
1
0.5
0.25
Cache Enabled
Cache Disabled
Cache Enabled
Cache Disabled
mA
IDD_IN
(AMP1)
32.5
32.3
28.5
23.5
18.3
14.2
12
6.1
2.1
1.1
0.65
0.38
0.25
0.14
IDD_I0
(AMP2)
0.28
0.28
0.28
0.28
0.28
0.28
0.28
0.1
0.1
0.1
0.1
0.1
0.1
0.1
IDD_CORE
(AMP3)
29
27.8
23.8
18.6
14.4
10.8
8.3
3.6
2
1
0.61
0.35
0.24
0.13
IDD_IN
(AMP1)
35
29.8
26.3
20.9
16.5
12.6
9.5
4.2
2.85
1.5
0.82
0.47
0.3
0.16
IDD_I0
(AMP2)
2
1.75
1.68
1.5
1.4
1.2
1.1
0.9
0.8
0.6
0.4
0.25
0.18
0.1
IDD_CORE
(AMP3)
30
27
24
19.3
15.3
10.9
8.25
4
2.8
1.45
0.8
0.45
0.28
0.14
IDD_IN
(AMP1)
31.2
26.4
22.3
17.2
13
9.8
7.4
3.1
2.1
1.2
0.65
0.38
0.25
0.15
IDD_I0
(AMP2)
0.28
0.28
0.28
0.28
0.28
0.28
0.28
0.1
0.1
0.1
0.1
0.1
0.1
0.1
IDD_CORE
(AMP3)
28
23.6
20
15.6
11.8
8.15
6.2
3.1
2.1
1.2
0.6
0.37
0.23
0.12
IDD_IN
(AMP1)
30.8
27
24
19.7
16
12.5
9.4
4.2
2.8
1.5
0.8
0.47
0.3
0.16
IDD_I0
(AMP2)
1.8
1.7
1.7
1.6
1.5
1.4
1.2
1.1
1
0.9
0.66
0.38
0.25
0.15
IDD_CORE
(AMP3)
27.4
24.3
21.8
18
14.7
10.6
8.2
4.2
2.7
1.4
0.75
0.4
0.28
0.13