516
SAM4CP [DATASHEET]
43051E–ATPL–08/14
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests
access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and transfers the data
to the Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data depending on its
mechanism.
28.4.5 PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC returns flags to the
peripheral. All these flags are only visible in the Peripheral Status Register.
Depending on whether the peripheral is half- or full-duplex, the flags belong to either one single channel or two different
channels.
28.4.5.1 Receive Transfer End
The receive transfer end flag is set when PERIPH_RCR reaches zero and the last data has been transferred to memory.
This flag is reset by writing a non-zero value to PERIPH_RCR or PERIPH_RNCR.
28.4.5.2 Transmit Transfer End
The transmit transfer end flag is set when PERIPH_TCR reaches zero and the last data has been written to the
peripheral THR.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
28.4.5.3 Receive Buffer Full
The receive buffer full flag is set when PERIPH_RCR reaches zero, with PERIPH_RNCR also set to zero and the last
data transferred to memory.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
28.4.5.4 Transmit Buffer Empty
The transmit buffer empty flag is set when PERIPH_TCR reaches zero, with PERIPH_TNCR also set to zero and the last
data written to peripheral THR.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
28.5
Peripheral DMA Controller (PDC) User Interface
Note:
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the
user depending on the function and the desired peripheral.
Table 28-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Receive Pointer Register
PERIPH
(1)
_RPR
Read/Write
0
0x04
Receive Counter Register
PERIPH_RCR
Read/Write
0
0x08
Transmit Pointer Register
PERIPH_TPR
Read/Write
0
0x0C
Transmit Counter Register
PERIPH_TCR
Read/Write
0
0x10
Receive Next Pointer Register
PERIPH_RNPR
Read/Write
0
0x14
Receive Next Counter Register
PERIPH_RNCR
Read/Write
0
0x18
Transmit Next Pointer Register
PERIPH_TNPR
Read/Write
0
0x1C
Transmit Next Counter Register
PERIPH_TNCR
Read/Write
0
0x20
Transfer Control Register
PERIPH_PTCR
Write-only
0
0x24
Transfer Status Register
PERIPH_PTSR
Read-only
0