167
SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.6.11.16 VMOV ARM Core Register to Single Precision
Transfers a single-precision register to and from an ARM core register.
Syntax
VMOV{
cond
}
Sn
,
Rt
VMOV{
cond
}
Rt
,
Sn
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Sn
is the single-precision floating-point register.
Rt
is the ARM core register.
Operation
This instruction transfers:
The contents of a single-precision register to an ARM core register.
The contents of an ARM core register to a single-precision register.
Restrictions
Rt
cannot be PC or SP.
Condition Flags
These instructions do not change the flags.
12.6.11.17 VMOV Two ARM Core Registers to Two Single Precision
Transfers two consecutively numbered single-precision registers to and from two ARM core registers.
Syntax
VMOV{
cond
}
Sm
,
Sm1
,
Rt
,
Rt2
VMOV{
cond
}
Rt
,
Rt2
,
Sm
,
Sm
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Sm
is the first single-precision register.
Sm1
is the second single-precision register.
This is the next single-precision register after
Sm
.
Rt
is the ARM core register that
Sm
is transferred to or from.
Rt2
is the The ARM core register that
Sm1
is transferred to or from.
Operation
This instruction transfers:
The contents of two consecutively numbered single-precision registers to two ARM core registers.
The contents of two ARM core registers to a pair of single-precision registers.
Restrictions
The restrictions are:
The floating-point registers must be contiguous, one after the other.
The ARM core registers do not have to be contiguous.
Rt
cannot be PC or SP.
Condition Flags
These instructions do not change the flags.