SAM4CP [DATASHEET]
43051E–ATPL–08/14
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8.
Memories
The memory map shown in
Figure 7-1, “Memory Mapping of Code and SRAM area”
is global to both Cortex-M4
processors except the “Boot Memory” block. For more information on Boot Memory please refer to
Section 8.1.5 “Boot
Strategy” on page 36
.
Each processor uses its own ARM private bus memory map for the NVIC and other system functions.
8.1
Embedded Memories
8.1.1
Internal SRAM
The SAM4CP embeds a total of 152 Kbytes high-speed SRAM with zero wait state access time.
SRAM0 on Matrix0 is 128 Kbytes. It is dedicated to the application processor (CM4P0) or other peripherals on Matrix0
but can be identified and used by masters on Matrix1. Please refer to “Bus Matrix (MATRIX)” section of this datasheet for
more details.
SRAM1 on Matrix1 is 16 Kbytes. It is mainly dedicated to be the code region of the CM4P1 processor but can be
identified and used by on Matrix0. Please refer to “Bus Matrix (MATRIX)” section of this datasheet for more details.
SRAM2 on Matrix1 is 8 Kbytes. It is mainly dedicated to be the data region of the CM4P1 processor or other peripherals
on Matrix1 but can be identified and used by masters on Matrix0. Please refer to “Bus Matrix (MATRIX)” section of this
datasheet for more details.
If the CM4P1 processor is in the reset state and not used, the application core can use it.
The SRAM is located in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF_FFFF.
8.1.2
System ROM
The SAM4CP embeds an Internal ROM for the master processor (CM4P0), which contains the SAM Boot Assistant
(SAM-BA), In Application Programming routines (IAP), and Fast Flash Programming Interface (FFPI).
The ROM is always mapped at the address 0x02000000.
8.1.3
CPKCC ROM
The ROM contains a Cryptographic Library using the CPKCC Cryptographic accelerator peripheral (CPKCC) to provide
support for Rivest Shamir Adleman (RSA), Elliptic Curve Cryptography (ECC), Digital Signature Algorithm (DSA) and
Elliptic Curve Digital Signature Algorithm (ECDSA).
8.1.4
Embedded Flash
8.1.4.1 Flash Overview
The embedded Flash is the boot memory for the Cortex-M4 Core 0 (CM4P0).
The flash memory can be accessed through the Cache Memory Controller (CMCC0) of the CM4P0 and can also be
identified by the Cortex-M4F Core 1 (CM4P1) through its Cache Memory Controller (CMCC1).
The memory plane is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64 Kbytes is divided
into 3 smaller sectors.
The three smaller sectors are organized into 2 sectors of 8 Kbytes and 1 sector of 48 Kbytes. Refer to
Figure 8-1
below.
The Flash Memory has a Built-in Error Code Correction provides 2-bit error detection and 1-bit correction per 128 bits.