109
SAM4CP [DATASHEET]
43051E–ATPL–08/14
The CMP instruction subtracts the value of
Operand2
from the value in
Rn
. This is the same as a SUBS instruction,
except that the result is discarded.
The CMN instruction adds the value of
Operand2
to the value in
Rn
. This is the same as an ADDS instruction, except that
the result is discarded.
Restrictions
In these instructions:
Do not use PC
Operand2
must not be SP.
Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples
CMP
CMN
CMPGT
R2, R9
R0, #6400
SP, R7, LSL #2
12.6.5.6 MOV and MVN
Move and Move NOT.
Syntax
MOV{S}{
cond
}
Rd
,
Operand2
MOV{
cond
}
Rd
, #
imm16
MVN{S}{
cond
}
Rd
,
Operand2
where:
S
is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see
“Conditional Execution”
.
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
Operand2
is a flexible second operand. See
“Flexible Second Operand”
for details of the options.
imm16
is any value in the range 0-65535.
Operation
The MOV instruction copies the value of
Operand2
into
Rd
.
When
Operand2
in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n.
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if
n
!= 0.
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n.
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n.
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of
Operand2
as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs.
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs.
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs.
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs.
See
“ASR, LSL, LSR, ROR, and RRX”
.
The MVN instruction takes the value of
Operand2
, performs a bitwise logical NOT operation on the value, and places the
result into
Rd
.