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型號(hào)：	E5550F-DOW
廠商：	ATMEL CORP
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁(yè)數(shù)：	908/1069頁(yè)
文件大小：	14303K
代理商：	E5550F-DOW

SAM4CP [DATASHEET]

43051E–ATPL–08/14

Functional Description

40.6.1 Analog-to-digital Conversion

The ADC uses the ADC clock to perform conversions. Converting a single analog value to a 10-bit digital data requires

tracking clock cycles as defined in the field TRACKTIM of the

“ADC Mode Register” on page 920

. The ADC clock

frequency is selected in the PRESCAL field of ADC_MR.

The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to 255 (0xFF). PRESCAL

must be programmed in order to provide an ADC clock frequency according to the parameters given in the Electrical

Characteristics section.

Figure 40-2.

Sequence of ADC conversions

40.6.2 Conversion Reference

The conversion is performed on a full range between 0V and the reference voltage. The reference voltage is defined by

the external pin ADVREF, or programmed using the internal reference voltage that is configured in ADC_ACR. Analog

inputs between these voltages convert to values based on a linear conversion.

40.6.3 Conversion Resolution

The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the LOWRES bit in ADC_MR. By

default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the

LOWRES bit, the ADC switches to the lowest resolution and the conversion results can be read in the lowest significant

bits of the data registers. The two highest bits of the DATA field in the corresponding Channel Data register (ADC_CDR)

and of the LDATA field in the Last Converted Data register (ADC_LCDR) read 0.

40.6.4 Conversion Results

When a conversion is completed, the resulting 10-bit digital value is stored in ADC_CDRx of the current channel and in

ADC_LCDR. By setting the TAG option in the Extended Mode register (ADC_EMR), ADC_LCDR presents the channel

number associated with the last converted data in the CHNB field.

The EOCx bit and DRDY in the Interrupt Status register (ADC_ISR) are set. In the case of a connected PDC channel,

DRDY rising triggers a data request. In any case, both EOC and DRDY can trigger an interrupt.

Reading one ADC_CDR clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit.

Start Up Time

(and tracking of CH0)

Conversion of CH0

Conversion of CH1

Tracking of CH1

Tracking of CH2

Trigger event

(Hard or Soft)

相關(guān)PDF資料	PDF描述
E5530H-230-S8	SPECIALTY TELECOM CIRCUIT, PDSO8
E5530H-230-DOW	SPECIALTY TELECOM CIRCUIT, UUC
ECM2A5C3A12-29.939MTR	QUARTZ CRYSTAL RESONATOR, 29.939 MHz
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ED1702N	NPN general purpose transistor

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5550F-S8	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder

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