982
SAM4CP [DATASHEET]
43051E–ATPL–08/14
42.5.2 ICM Hash Area
The ICM Hash Area is a contiguous Area of system memory that the controller and the processor can access. The
physical location is configured in the ICM hash area start address register. This address is a multiple of 128 bytes. If the
CDWBN bit of the context register is cleared (i.e. Write Back activated), the ICM controller performs a digest write
operation at the following starting location: *(ICM_HASH) + (RID<<5), where RID is the current region context identifier. If
the CDWBN bit of the context register is set (i.e. Digest Comparison activated), the ICM controller performs a digest read
operation at the same address.
42.5.2.1 Message Digest Example
Considering the following
512 bits message
(example given in FIPS 180-2):
“6162638000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000018”
The message is written to memory in a Little Endian (LE) system architecture.
The digest is stored at the memory location pointed at by the ICM_HASH pointer with a Region Offset.
Table 42-3.
512 bits Message Memory Mapping
Memory
Address
Address Offset / Byte Lane
0x3 / 31:24
0x2 / 23:16
0x1 / 15:8
0x0 / 7:0
0x000
80
63
62
61
0x004 - 0x038
00
00
00
00
0x03C
18
00
00
00
Table 42-4.
LE Resulting SHA-160 Message Digest Memory Mapping
Memory
Address
Address Offset / Byte Lane
0x3 / 31:24
0x2 / 23:16
0x1 / 15:8
0x0 / 7:0
0x000
36
3e
99
a9
0x004
6a
81
06
47
0x008
71
25
3e
ba
0x00C
6c
c2
50
78
0x010
9d
d8
d0
9c
Table 42-5.
Resulting SHA-224 Message Digest Memory Mapping
Memory
Address
Address Offset / Byte Lane
0x3 / 31:24
0x2 / 23:16
0x1 / 15:8
0x0 / 7:0
0x000
22
7d
09
23
0x004
22
d8
05
34
0x008
77
a4
42
86
0x00C
b3
55
a2
bd
0x010
e4
bc
ad
2a
0x014
f7
b3
a0
bd
0x018
a7
9d
6c
e3