110
SAM4CP [DATASHEET]
43051E–ATPL–08/14
The MOVW instruction provides the same function as MOV, but is restricted to using the
imm16
operand.
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift.
The S suffix must not be specified.
When
Rd
is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored.
A branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction
to branch for software portability to the ARM instruction set.
Condition Flags
If S is specified, these instructions:
Update the N and Z flags according to the result.
Can update the C flag during the calculation of
Operand2
, see
“Flexible Second Operand”
.
Do not affect the V flag.
Examples
MOVS R11, #0x000B
MOV R1, #0xFA05
MOVS R10, R12
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
; Write value of 0x000B to R11, flags get updated
; Write value of 0xFA05 to R1, flags are not updated
; Write value in R12 to R10, flags get updated
12.6.5.7 MOVT
Move Top.
Syntax
MOVT{
cond
}
Rd
, #
imm16
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
imm16
is a 16-bit immediate constant.
Operation
MOVT writes a 16-bit immediate value,
imm16
, to the top halfword,
Rd
[31:16], of its destination register. The write does
not affect
Rd
[15:0].
The MOV, MOVT instruction pair enables to generate any 32-bit constant.
Restrictions
Rd
must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.