326
SAM4CP [DATASHEET]
43051E–ATPL–08/14
20.3
Block Diagram
Figure 20-1.
Supply Controller Block Diagram
Supply Monitoring
Power-On-Reset
VDDCORE
VDDBU
VDDOUT
SHDN
VDDLCD
(In/Out)
Core Voltage
Regulator
VROFF
ONREG
VDDIN
LCD Voltage
Regulator
LCDMODE
- OFF (LCDOFF),
- Active (LCDON_EXTVR),
- Hi-Z (LCDON_EXTVR)
LCDVROUT
VDDLCD
Adjust
Backup
Mode
Used/Unused
Automatic
Power Switch
Note:
TMPx signals and WKUPx signals are multiplexed on the same pins (ex. TMP0/WKUP0, TMP1/WKUP10, etc.).
This generates a wake-up event only, a tamper event only or a wake-up and a tamper event.
RSTC
Module
vddcore_nreset (system reset signal)
core_backup_reset
VDDBU_SW
reset enable
disable
Brownout
Detector
VDDCORE
Programmable
Supply Monitor
VDDIO
Zero-Power
Power-On-Reset
VDDBU_SW
threshold
enable
sampling period
reset enable
interrupt enable
wake-up enable
VDDIO
XTALSEL
SLCK (Slow Clock)
PORCORE_out
BODCORE_out
SMIO_out
PORBUSW_out
SMEN
SMIEN
SMRSTEN
SMSMPL
SMTH
BUPPOREN
BODRSTEN
BODDIS
Wake-Up & Tamper Inputs
TIMSTPM3DIS
TIMSTPM2DIS
TIMSTPM1DIS
TimeStamp
Disable
RTC
Module
WKUPx
x:1..15
WKUPDBC
WKUPEN[1..15]
Programmable
Debouncer
wake-up
TMP1/2/3
LPDBC
LPDBCEN[1..3]
Programmable
LP Debouncer
tamper
WKUP0
WKUPDBC
WKUPEN0
Programmable
Debouncer
wake-up
TMP0
LPDBC
LPDBCEN0
Programmable
LP Debouncer
tamper
FWUP
FWUPDBC
FWUPEN
Programmable
Debouncer
wake-up
Clear on
tamper event
(8/16)
LPDBCCLR
LPDBDISCLR1
LPDBDISCLR2
LPDBDISCLR3
General
Purpose
Backup
Registers
x8
x8
Supplied by
VDDCORE
Supplied by
VDDBU_SW
Supplied by
VDDIO
Supplied by
VDDIN
SUPPLY CONTROLLER
RTT
Module
RTTEN
wake-up
RTCEN
wake-up
RC OSC 32kHz
OSCBYPASS
XTAL OSC 32kHz
Slow Clock Control
I/O pin referred to VDDBU
I/O pin referred to VDDIO