648
SAM4CP [DATASHEET]
43051E–ATPL–08/14
33.7
Functional Description
33.7.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (SPI_MR):
The pins NPCS0 to NPCS3 are all configured as outputs
The SPCK pin is driven
The MISO line is wired on the receiver input
The MOSI line is driven as an output by the transmitter.
The SPI operates in Slave mode if the MSTR bit in the SPI_MR is written to 0:
The MISO line is driven by the transmitter output
The MOSI line is wired on the receiver input
The SPCK pin is driven by the transmitter to synchronize the receiver.
The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS).
The pins NPCS0 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only
in Master Mode.
33.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the SPI Chip Select Register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These two
parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters
has two possible states, resulting in four possible combinations that are incompatible with one another. Consequently, a
master/slave pair must use the same parameter pair values to communicate. If multiple slaves are connected and require
different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 33-4
shows the four modes and corresponding parameter settings.
Table 33-4.
SPI Bus Protocol Mode
SPI Mode
CPOL
NCPHA
Shift SPCK Edge
Capture SPCK Edge
SPCK Inactive Level
0
0
1
Falling
Rising
Low
1
0
0
Rising
Falling
Low
2
1
1
Rising
Falling
High
3
1
0
Falling
Rising
High