參數(shù)資料
型號(hào): EVAL-ADAU1442EBZ
廠商: Analog Devices Inc
文件頁數(shù): 10/93頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻,音頻處理
嵌入式: 是,DSP
已用 IC / 零件: ADAU1442
主要屬性: 單芯片多通道 28/56 位音頻 DSP
次要屬性: I²C & SPI 接口
已供物品: 電路板,線纜,說明文檔,GPIO 子板,電源
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 17 of 92
THEORY OF OPERATION
SYSTEM BLOCK DIAGRAM
1.8V REGULATOR
28-/56-BIT, 172MHz
PROGRAMMABLE AUDIO
PROCESSOR CORE,
170ms DELAY MEMORY
S/PDIF
TRANSMITTER
S/PDIF
RECEIVER
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
INPUT PORT
(×9)
SERIAL CLOCK
DOMAINS
(×12)
CLOCK
OSCILLATOR
SERIAL DATA
OUTPUT PORT
(×9)
MP
AUXILIARY
ADC
RESET
CLOCK
OUTPUT
PLL
I2C/SPI CONTROL
INTERFACE
AND SELF-BOOT
DVDD
DGND
AVDD
AGND
XTALI, XTALO
RESET
IOVDD
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
MP[11:4]
SPI/I2C* SELFBOOT
CLKMODE[1:0]
PVDD
PGND
SPDIFI
SPDIFO
CLKOUT
MP[3:0]/
ADC[3:0]
FLE
X
IB
LE
A
U
D
IO
R
OU
TIN
G
M
A
TR
IX
(I
N
PU
T
SI
D
E)
+3.3V VDRIVE
3 TO 9
PLL[2:0]
PLL_FILT
FLE
X
IB
LE
A
U
D
IO
R
OU
TIN
G
M
A
TR
IX
(O
U
T
PU
T
SI
D
E)
2
3
4
8
5
2
9
8
6
3 TO 9
07696-
008
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
*SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
ADAU1442/
ADAU1445/
ADAU1446
Figure 8. System Block Diagram
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