參數(shù)資料
型號(hào)： EVAL-ADAU1442EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 52/93頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 電路板，線纜，說明文檔，GPIO 子板，電源
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 55 of 92
ASRC Output Rate Select Pairs[7:0] Registers (Address 0xE088 to Address 0xE08F)
Table 34. Bit Descriptions of ASRC Output Rate Select Pairs[7:0] Registers
Bit Position
Description
Default
[15:6]
Reserved
[5:0]
ASRC output rate
111111
000000 = Serial Output Pair 0 (Channel 0, Channel 1)
000001 = Serial Output Pair 1 (Channel 2, Channel 3)
000010 = Serial Output Pair 2 (Channel 4, Channel 5)
000011 = Serial Output Pair 3 (Channel 6, Channel 7)
000100 = Serial Output Pair 4 (Channel 8, Channel 9)
000101 = Serial Output Pair 5 (Channel 10, Channel 11)
000110 = Serial Output Pair 6 (Channel 12, Channel 13)
000111 = Serial Output Pair 7 (Channel 14, Channel 15)
001000 = Serial Output Pair 8 (Channel 16, Channel 17)
001001 = Serial Output Pair 9 (Channel 18, Channel 19)
001010 = Serial Output Pair 10 (Channel 20, Channel 21)
001011 = Serial Output Pair 11 (Channel 22, Channel 23)
010000 = DSP rate
010001 = internal fS,NORMAL rate
010010 = internal fS,DUAL rate
010011 = internal fS,QUAD rate
111111 = no rate
ASRC Output Rate Bits (Bits[5:0])
These bits select the output conversion rate for the eight ASRCs.
Any asynchronous input to the ASRC is output at this rate. It
can be set by one of the 12 serial output channel pairs’ fS clock
signals (the LRCLK associated with their automatically assigned
serial port) or by the core’s fS,NORMAL, fS,DUAL, or fS,QUAD clock signals.
In the case of the ADAU1442, each output from the stereo
ASRCs can have a separate data output.
In the case of the ADAU1445, each output from the stereo
ASRCs can have a separate data output; however, all outputs
from Stereo ASRC[3:0] must be synchronous to each other, and
all outputs from Stereo ASRC[7:4] must be synchronous to each
other. The first group of ASRCs (Stereo ASRC[3:0]) takes its
output rate from the setting on the Stereo ASRC 0 output. The
output rate for Stereo ASRC[3:1] is automatically set to this rate,
ignoring the settings for the Stereo ASCR[3:1] outputs. The second
group of ASRCs (Stereo ASRC[7:4]) takes its output rate from the
setting on the Stereo ASRC 4 output. The output rate for Stereo
ASRC[7:5] is automatically set to this rate, ignoring the settings
for the Stereo ASRC[7:5] outputs.
In the case of the ADAU1446, which contains no ASRCs, these
registers do not affect system operation in any way and can be
ignored.
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