參數(shù)資料
型號(hào): EVAL-ADAU1442EBZ
廠商: Analog Devices Inc
文件頁數(shù): 27/93頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻,音頻處理
嵌入式: 是,DSP
已用 IC / 零件: ADAU1442
主要屬性: 單芯片多通道 28/56 位音頻 DSP
次要屬性: I²C & SPI 接口
已供物品: 電路板,線纜,說明文檔,GPIO 子板,電源
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 32 of 92
Table 19. Configurations for Standard Audio Data Formats
Format
LRCLK Polarity
LRCLK Type
BCLK Polarity
MSB Position
I2S
Frame begins on
falling edge
Clock
Data changes on falling edge
Delayed from LRCLKx edge by 1 BCLK
Left-Justified
Frame begins on
rising edge
Clock
Data changes on falling edge
Aligned with LRCLKx edge
Right-Justified
Frame begins on
rising edge
Clock
Data changes on falling edge
Delayed from LRCLKx edge by 8, 12, or 16 BCLKs
TDM with Clock
Frame begins on
falling edge
Clock
Data changes on falling edge
Delayed from start of frame clock by 1 BCLK
TDM with Pulse
Frame begins on
rising edge
Pulse
Data changes on falling edge
Delayed from start of frame clock by 1 BCLK
DSP CORE
SERIAL
OUTPUT
PORTS
(×9)
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
SERIAL
INPUT
PORTS
(×9)
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
DEDICATED
INPUT
CLOCK DOMAINS
(×3)
DEDICATED
OUTPUT
CLOCK DOMAINS
(×3)
ASSIGNABLE
INPUT/OUTPUT
DOMAINS
(×6)
0 TO 2
3 TO 8
BCL
K3/
L
RCL
K3
BCL
K4/
L
RCL
K4
BCL
K5/
L
RCL
K5
BCL
K6/
L
RCL
K6
BCL
K7/
L
RCL
K7
BCL
K8/
L
RCL
K8
9 TO 11
BCL
K9/
L
RCL
K9
BCL
K10/
L
RCL
K10
BCL
K11/
L
RCL
K11
18:2
(×9)
18:2
(×9)
CLOCK PAD
MULTIPLEXERS
INPUT
CLOCK DOMAIN
SELECTOR
OUTPUT
CLOCK DOMAIN
SELECTOR
SERIAL
INPUT
MODES
SERIAL
OUTPUT
MODES
0
1
2
3
4
5
6
7
8
3
4
5
6
7
8
9
10 11
AND
FARM
4:2
2
BCL
K0/
L
RCL
K0
BCL
K1/
L
RCL
K1
BCL
K2/
L
RCL
K2
2
07696-
030
Figure 21. Overview of Serial Data Input/Output Ports
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