- 您現在的位置：買賣IC網 > PDF目錄16427 > EVAL-ADAU1442EBZ (Analog Devices Inc)BOARD EVAL FOR ADAU1442 PDF資料下載
參數資料
| 型號： | EVAL-ADAU1442EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 17/93頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1442 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1442 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 電路板，線纜，說明文檔，GPIO 子板，電源 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 23 of 92
PLL Loop Filter
The PLL loop filter should be connected to the PLL_FILT pin. This
filter, shown in Figure 11, includes three passive components—
two capacitors and a resistor. The values of these components
do not need to be exact; the tolerance can be up to 10% for the
resistor and up to 20% for each capacitor. The 3.3 V signal shown
in the schematic can be connected to the PVDD supply of the chip.
1.5k
Ω
PLL_FILT
33nF
1.8nF
PVDD
07696-
011
ADAU1442/
ADAU1445/
ADAU1446
Figure 11. PLL Loop Filter
as Clock Masters
ADAU1446 to other chips in the system, the CLKOUT pin is
used. To set the frequency of this clock signal, the CLKMODEx
pins must be set (see Table 10).
Table 10. CLKOUT Modes
CLKOUT Signal
CLKMODE1
CLKMODE0
Disabled
0
Buffered Oscillator
0
1
256 × fS,NORMAL
1
0
512 × fS,NORMAL
1
Master Clock and PLL Modes and Settings
DSP Core Rate Select Register (Address 0xE220)
The core’s start pulse initiates the operation of the core and
determines the sample rate of signals processed inside the core.
This pulse can originate from one of three internally generated
fS signals (fS,NORMAL, fS,DUAL, or fS,QUAD), one of the 12 serial input fS
signals (an LRCLK signal associated with a serial input port),
one of the 12 serial output fS signals (an LRCLK signal associated
with a serial output port), or LRCLK recovered from the S/PDIF
receiver input.
Setting the value of the DSP core rate select register sets the speed
of the DSP core (see Table 12). By default, the signals processed
in the core are at the normal DSP core rate; therefore, the core
clock is 3584 × fS,NORMAL. For a system processing signals in the
core at the dual rate, the start pulse should be set to the internally
generated dual rate, and the core clock is 1792 × fS,DUAL. For a
system processing signals in the core at the quad rate, the start
pulse should be set to the internally generated quad rate, and
the core clock is 896 × fS,QUAD.
Master Clock Enable Switch Register (Address 0xE280)
For power-saving purposes, various parts of the chip can be
switched on and off. Setting the appropriate bit to 0 disables the
corresponding subsystem, and setting the bit to 1 enables the
subsystem. This is the first register that should be set after the
device is powered on and completes its initialization. Failure to
set this register may compromise future register writes.
Table 11. Bit Descriptions of Register 0xE280
Bit Position
Description1
Default
[15:9]
Reserved
8
Enable MCLK to auxiliary ADCs
0
7
Enable MCLK to S/PDIF transmitter
0
6
Enable MCLK to S/PDIF receiver
0
5
Enable MCLK to DSP core
0
4
Enable MCLK to Stereo ASRC[7:4]2
0
3
Enable MCLK to Stereo ASRC[3:0]2
0
2
Enable MCLK to serial outputs
0
1
Enable MCLK to serial inputs
0
Enable MCLK to flexible audio routing
matrix (FARM)
0
1
0 = disable, 1 = enable.
2
See the Flexible Audio Routing Matrix—Input Side section for more information.
相關PDF資料 |
PDF描述 |
|---|---|
| A3AAH-4036G | IDC CABLE - ASC40H/AE40G/ASC40H |
| AMIS30622C6227RG | IC MOTOR DVR MICROSTP I2C 20SOIC |
| A1CXB-3036M | IDC CABLE- AKC30B/AE30M/X |
| VE-214-EX | CONVERTER MOD DC/DC 48V 75W |
| GCC10DRYH-S734 | CONN EDGECARD 20POS DIP .100 SLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EVAL-ADAU1446EBZ | 功能描述:BOARD EVAL FOR ADAU1446 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1590EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADAU1592EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADAU1592 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| EVAL-ADAU1701EB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR SIGMADSP AUDIO PROCESSOR - Bulk |
| EVAL-ADAU1701EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。