參數(shù)資料
型號(hào)： EVAL-ADAU1442EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/93頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 電路板，線纜，說明文檔，GPIO 子板，電源
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 37 of 92
SERIAL INPUT PORTS
The serial input ports convert standard I2S and TDM signals into
16-, 20-, and 24-bit audio signals for input to the audio processor.
They support TDM2, TDM4, TDM8, and TDM16 time division
multiplexing schemes and I2S, left-justified, right-justified, MSB
delay-by-12 and delay-by-16 modes. Different clock polarities
and multiple word lengths are supported, as well as the capability
to drive in master mode or to be driven in slave mode.
The serial input ports are composed of up to nine clock domains
(Clock Domain 0 to Clock Domain 8) and up to nine serial data
signals (SDATA_IN0 to SDATA_IN8).
In slave mode, the nine serial input clock domains are driven
directly from the corresponding nine pairs of LRCLKx and
BCLKx pins on the IC. Three pairs of LRCLKx and BCLKx
pins (LRCLK[2:0] and BCLK[2:0]) are hardwired to Clock
Domains[2:0], which are serial inputs. The remaining six pairs
of LRCLKx and BCLKx pins (LRCLK[8:3] and BCLK[8:3]) are
multiplexed to Clock Domains[8:3] as either inputs or outputs.
The multiplexer can be set to use these signals as input clock
domains by writing to Bits[5:0] of the clock pad multiplexer
register (Address 0xE240) as explained in Table 23. This
configuration is also valid in master mode.
Figure 30 shows in more detail how the clocks are routed to and
from the serial input ports. For the assignable clock domains
(Clock Domains[8:3]), the clock pad multiplexer allows them to
be routed either to the serial input ports or to the serial output
ports independently. In slave mode, the clock domain selector
(that is, the 18:2 multiplexer) allows each serial input port to
clock from any available clock domain. In master mode, the
clock domain selector is bypassed, and the assignments described
The maximum number of audio channels that can be input to
SigmaDSP is 24. The serial input ports must be set in a way that
respects this (for example, two TDM16 streams is not a valid entry).
Table 23. Input Clock Domain Multiplexing
Clock Domain
Chip Pins
Register 0xE240 Setting
0
LRCLK0, BCLK0
N/A
1
LRCLK1, BCLK1
N/A
2
LRCLK2, BCLK2
N/A
3
LRCLK3, BCLK3
Set Bit 0 to 0
4
LRCLK4, BCLK4
Set Bit 1 to 0
5
LRCLK5, BCLK5
Set Bit 2 to 0
6
LRCLK6, BCLK6
Set Bit 3 to 0
7
LRCLK7, BCLK7
Set Bit 4 to 0
8
LRCLK8, BCLK8
Set Bit 5 to 0
Table 24. Input Clock Domain Assignments in Master Mode
Data Pin
Clock Pins
SDATA_IN0
LRCLK0, BCLK0
SDATA_IN1
LRCLK1, BCLK1
SDATA_IN2
LRCLK2, BCLK2
SDATA_IN3
LRCLK3, BCLK3
SDATA_IN4
LRCLK4, BCLK4
SDATA_IN5
LRCLK5, BCLK5
SDATA_IN6
LRCLK6, BCLK6
SDATA_IN7
LRCLK7, BCLK7
SDATA_IN8
LRCLK8, BCLK8
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