參數(shù)資料
型號: EVAL-ADAU1442EBZ
廠商: Analog Devices Inc
文件頁數(shù): 46/93頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1442
標準包裝: 1
系列: SigmaDSP®
主要目的: 音頻,音頻處理
嵌入式: 是,DSP
已用 IC / 零件: ADAU1442
主要屬性: 單芯片多通道 28/56 位音頻 DSP
次要屬性: I²C & SPI 接口
已供物品: 電路板,線纜,說明文檔,GPIO 子板,電源
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 49 of 92
Stereo ASRC Routing Overview
Within the ADAU1442 and ADAU1445, signals are required to
be synchronous to the master clock only when they are within
the DSP core itself. At all other times, signals can be asynchronous
to one another and the core. This is illustrated in Figure 42.
Because the ADAU1446 has no ASRCs, all audio signals must
be synchronous at all times.
The stereo ASRCs allow asynchronous signals to be converted
for processing in the DSP.
The input to an ASRC can come from one of 21 sources: the
12 input channel pairs, the S/PDIF Rx pair, or the eight DSP-to-
ASRC pairs. This allows the ASRCs to be placed both before
and after the DSP. Figure 43 and Figure 44 show examples of
how the ASRCs can be used both before and after the DSP.
RATE
8
STEREO
ASRCs
(8 × 2 CH)
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
TO DSP
TO FARM
(OUTPUT SIDE)
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
FROM DSP
FROM SERIAL
INPUT PORTS
FROM
S/PDIF Rx
07696-
043
FARM
Figure 41. Stereo ASRC Routing
SYNCHRONOUS
ASYNCHRONOUS
07696-
042
Figure 42. Synchronous and Asynchronous Zones of the ADAU1442 and ADAU1445
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