參數(shù)資料
型號(hào)： EVAL-ADAU1442EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 59/93頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 電路板，線纜，說(shuō)明文檔，GPIO 子板，電源
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 61 of 92
Numeric Formats
DSP systems commonly use a standard numeric format.
Fractional number systems are specified by an A.B format,
where A is the number of bits to the left of the decimal point
and B is the number of bits to the right of the decimal point.
The ADAU1442/ADAU1445/ADAU1446 use the same numeric
format for both the parameter and data values. The format is as
shown in the Numerical Format: 5.23 section.
Numerical Format: 5.23
Linear range: –16.0 to (+16.0 1 LSB)
Examples:
1000 0000 0000 0000 0000 0000 0000 = 16.0
1110 0000 0000 0000 0000 0000 0000 = 4.0
1111 1000 0000 0000 0000 0000 0000 = 1.0
1111 1110 0000 0000 0000 0000 0000 = 0.25
1111 1111 0011 0011 0011 0011 0011 = 0.1
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)
0000 0000 0000 0000 0000 0000 0000 = 0.0
0000 0000 1100 1100 1100 1100 1101 = 0.1
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 – 1 LSB).
The serial port accepts up to 24 bits of input and is sign-
extended to the full 28 bits of the DSP core. This allows internal
gains of up to 24 dB without encountering internal clipping.
A digital clipper circuit is used within the DSP core before
outputting to the serial port outputs, ASRCs, and S/PDIF
transmitter (see Figure 52). This clips the top four bits of the
signal to produce a 24-bit output with a range of 1.0 (minus
1 LSB) to –1.0. Figure 52 shows the maximum signal levels at
each point in the data flow in both binary and decibel levels.
4-BIT SIGN EXTENSION
SDATA_INx
1.23
(0dB)
1.23
(0dB)
1.23
(0dB)
5.23
(24dB)
5.23
(24dB)
SERIAL
PORT
SIGNAL
PROCESSING
(5.23 FORMAT)
DIGITAL
CLIPPER
07696-
053
Figure 52. Numeric Precision and Clipping Structure (TBD)
Programming
On power-up, the ADAU1442/ADAU1445/ADAU1446 have no
default program loaded. There are 3584 instruction cycles per
audio sample, resulting in an internal clock rate of 172.032 MHz
when fS,NORMAL is 48 kHz. The DSP runs in a stream-oriented
manner, meaning that all 3584 instructions are executed each
sample period. The ADAU1442/ADAU1445/ADAU1446 can also
be set up to accept dual- or quad-speed inputs by reducing the
number of instructions per sample. These modes can be set in
the core control register.
easily using SigmaStudio, an entirely graphical tool provided by
Analog Devices. No knowledge of writing line-level DSP code is
required, and the large library of predesigned algorithms should
drastically reduce development time. More information on
SigmaStudio can be found at the Analog Devices website.
Program Counter
The execution of instructions in the core is governed by a program
counter, which sequentially steps through the addresses of the
program RAM. The program counter starts every time a new
audio frame is clocked into the core. SigmaStudio inserts a
jump-to-start command at the end of every program. The
program counter increments sequentially until reaching this
command, and then jumps to the program start address
(Program RAM Address 0x2010) and waits for the next audio
frame to clock into the core.
Branching and Looping
Some cells in SigmaStudio can optionally modify the program
counter to implement simple branching and looping structures.
However, care must be taken that the program counter returns
to its starting address before a new frame is clocked. If the new
frame starts before the counter has returned to start, the audio
output is corrupted, and a reset is necessary.
The software compiler in SigmaStudio calculates the maximum
possible program cycles for a given project and generates an
error when a user exceeds the allowable limit.
DSP CORE MODES AND SETTINGS
Core Run Register (Address 0xE228)
Table 41. Descriptions of Register 0xE228
Bit Position
Description
Default
[15:1]
Reserved
0
Core run bit
0
This single-bit register initiates the run signal to start the core.
This should be the very last register that is set when the system
is initialized.
Before the core is halted, set the DSP core rate select register
(0xE220) to 0x001C. This disables the start pulse to the core.
Before the care is started, set the DSP Core Rate Select register
(0xE220) to the desired value. This enables the start pulse to the
core. Table 12 contains a list of valid settings.
If the core is halted (that is, if Bit 0 of Register 0xE228 is set to
0) during operation, the serial outputs jump immediately to 0.
This ensures that no dc level is left on the serial outputs and
helps prevent speaker damage in the system. It also allows the
system to mute and unmute all audio channels while minimizing
pops and clicks on the outputs.
The core run bit can be used to implement a system mute
functionality, as opposed to muting all of the individual
channels in software. However, this approach instantaneously
mutes the outputs, potentially causing clicks or pops on the
output. If a click- and pop-free mute is required, software slew
mute cells should be implemented into the DSP core’s signal
processing flow.
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