- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16427 > EVAL-ADAU1442EBZ (Analog Devices Inc)BOARD EVAL FOR ADAU1442 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADAU1442EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/93頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1442 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1442 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 電路板，線纜，說明文檔，GPIO 子板，電源 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 27 of 92
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition. The R/W bit determines the direction of the
data. A Logic 0 on the LSB of the first byte means that the master
writes information to the peripheral. A Logic 1 on the LSB of
the first byte means that the master reads information from the
peripheral. A data transfer takes place until a stop condition is
encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high. Figure 13 shows the
timing of an I2C write.
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous memory locations. This increment
happens automatically, unless a stop condition is encountered after
a single-word write. The registers and RAMs in the ADAU1445/
ADAU1446 range in width from one to five bytes; therefore, the
auto-increment feature knows the mapping between subaddresses
and the word length of the destination register (or memory lo-
cation). A data transfer is always terminated by a stop condition.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition.
If an invalid subaddress is issued by the user, the ADAU1442/
ADAU1445/ADAU1446 do not issue an acknowledge and return
to the idle condition. If the user exceeds the highest subaddress
while in auto-increment mode, one of two actions is taken. In
highest subaddress register contents until the master device issues a
no acknowledge, indicating the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the ninth
clock pulse on SCL. If the highest subaddress location is reached
while in write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by the
the idle condition.
I2C Read and Write Operations
Figure 15 shows the sequence of a single-word write operation.
issue an acknowledge by pulling SDA low.
Figure 16 shows the sequence of a burst mode write operation.
This figure shows an example in which the target destination
registers are two bytes. The ADAU1442/ADAU1445/
ADAU1446 know to increment the subaddress register every
two bytes because the requested subaddress corresponds to a
register or memory area with a 2-byte word length.
The sequence of a single-word read operation is shown in
Figure 17. Note that, even though this is a read operation, the
first R/W bit is a 0, indicating a write operation. This is because
the subaddress must be written to set up the internal address.
receipt of the subaddress, the master must issue a repeated start
command followed by the chip address byte with the R/W set to 1,
indicating a read operation. This causes the SDA pin of the
begin driving data back to the master. The master then responds
every ninth pulse with an acknowledge pulse to the ADAU1442/
Figure 18 shows the sequence of a burst mode read operation.
This figure shows an example in which the target read registers
the subaddress every two bytes because the requested subaddress
corresponds to a register or memory area with word lengths of
two bytes. Other address ranges can have a variety of word lengths,
ranging from one to five bytes; the ADAU1442/ADAU1445/
ADAU1446 always decode the subaddress and set the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
R/W
0
SCL
SDA
(CONTINUED)
SCL
(CONTINUED)
1
ADR
SEL
0
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
DATA BYTE 1
STOP BY
MASTER
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 2
07696-
013
ACK BY
ADAU1442/ADAU1445/ADAU1446
ACK BY
ADAU1442/ADAU1445/ADAU1446
ACK BY
ADAU1442/ADAU1445/ADAU1446
ACK BY
ADAU1442/ADAU1445/ADAU1446
Figure 13. I2C Write Clocking
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3AAH-4036G | IDC CABLE - ASC40H/AE40G/ASC40H |
| AMIS30622C6227RG | IC MOTOR DVR MICROSTP I2C 20SOIC |
| A1CXB-3036M | IDC CABLE- AKC30B/AE30M/X |
| VE-214-EX | CONVERTER MOD DC/DC 48V 75W |
| GCC10DRYH-S734 | CONN EDGECARD 20POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1446EBZ | 功能描述:BOARD EVAL FOR ADAU1446 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1590EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADAU1592EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADAU1592 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| EVAL-ADAU1701EB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR SIGMADSP AUDIO PROCESSOR - Bulk |
| EVAL-ADAU1701EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。